增加spi模式选择到顶层
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@@ -35,6 +35,7 @@ class ShinTopIO extends Bundle{
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val pllCtrl = Output(UInt(32.W))
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val xtal = Output(UInt(12.W))
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val spiSel = Output(UInt(2.W))
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}
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@@ -85,6 +86,7 @@ abstract class ShinTopBase extends Module{
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io.pllCtrl := interface.io.cReg.pllCtrl
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io.xtal := interface.io.cReg.xtal(11,0)
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io.spiSel := interface.io.cReg.spiSel
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val sram = Seq(
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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