diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 64a4445..45638a1 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -35,6 +35,7 @@ class ShinTopIO extends Bundle{
 
   val pllCtrl = Output(UInt(32.W))
   val xtal    = Output(UInt(12.W))
+  val spiSel  = Output(UInt(2.W))
 }
 
 
@@ -85,6 +86,7 @@ abstract class ShinTopBase extends Module{
 
   io.pllCtrl := interface.io.cReg.pllCtrl
   io.xtal    := interface.io.cReg.xtal(11,0)
+  io.spiSel  := interface.io.cReg.spiSel
 
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },