From b590ad79bc965b5befc0035bf3d6112f92d3cf88 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 11 Aug 2025 16:55:43 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0spi=E6=A8=A1=E5=BC=8F?= =?UTF-8?q?=E9=80=89=E6=8B=A9=E5=88=B0=E9=A1=B6=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/ShinTop.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 64a4445..45638a1 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -35,6 +35,7 @@ class ShinTopIO extends Bundle{ val pllCtrl = Output(UInt(32.W)) val xtal = Output(UInt(12.W)) + val spiSel = Output(UInt(2.W)) } @@ -85,6 +86,7 @@ abstract class ShinTopBase extends Module{ io.pllCtrl := interface.io.cReg.pllCtrl io.xtal := interface.io.cReg.xtal(11,0) + io.spiSel := interface.io.cReg.spiSel val sram = Seq( for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },