尝试速率配平，回环改到phy上

src/main/scala/backBoard/shin/SlaveRecParser.scala

@@ -28,14 +28,7 @@ class SlaveRecParser extends Module{
 
   val STATE_IDLE                = 0.U //空闲
   val STATE_HEADER              = 1.U //长度/ /保留2bits //包类型
-
-  val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
-
-  // val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
-  // val STATE_PAYLOAD_ADDR        = 3.U //子报文地址
-  // val STATE_PAYLOAD_OP_LENGTH   = 4.U //子报文命令类型 //子报文长度
-  // val STATE_PAYLOAD_WORKCNT     = 5.U //子报文工作计数
-
+  val STATE_SUBMSG_HEADER       = 2.U //子报文设备索引 //子报文类型
   val STATE_PAYLOAD_DATA        = 3.U //子报文数据
   val STATE_CRC                 = 4.U //CRC校验
   val STATE_ERROR               = 5.U //
@@ -48,10 +41,12 @@ class SlaveRecParser extends Module{
   io.isError := stateCurr === STATE_ERROR
   io.rec.ready := stateCurr =/= STATE_IDLE
   
-  crc.io.isEnable :=
+  crc.io.isEnable := io.rec.fire & (
     stateCurr === STATE_HEADER |
     stateCurr === STATE_SUBMSG_HEADER |
-    stateCurr === STATE_PAYLOAD_DATA
+    stateCurr === STATE_PAYLOAD_DATA    
+  )
+
 
   crc.io.dataIn := io.rec.bits.tdata
 
@@ -60,7 +55,7 @@ class SlaveRecParser extends Module{
   val crcData = Reg(UInt(32.W))
   val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
 
-  when( stateCurr === STATE_CRC ){
+  when( io.rec.fire & stateCurr === STATE_CRC ){
     crcData := Cat( crcData(23,0), io.rec.bits.tdata )
   }