diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index fb89801..a5d5196 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -114,7 +114,7 @@ trait CDRInAxis{ this: CDRInBase => val shiftData = Dualb4b5Decoder(checkSFD(9,0)) - val payloadLen = Reg(UInt(12.W)) + val payloadLen = RegInit(0.U(12.W)) when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ payloadLen := Cat( shiftData, 0.U(4.W) ) } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){ @@ -149,8 +149,8 @@ trait CDRInAxis{ this: CDRInBase => byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) assert( byteCnt <= (HeaderByte-1).U ) } .elsewhen( stateCurr === STATE_PAYLOAD ){ - byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U ) - assert( byteCnt <= ( payloadLen-1.U ) ) + byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U ) + assert( byteCnt <= ( payloadLen+ (4-1).U ) ) } } @@ -161,7 +161,7 @@ trait CDRInAxis{ this: CDRInBase => val axis_valid = RegInit(false.B) val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ) val axis_tuser = false.B - val axis_tlast = RegNext( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), false.B ) + val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B ) io.axis.valid := axis_valid io.axis.bits.tdata := axis_tdata diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index e8cf7a2..d5c44d1 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -72,9 +72,15 @@ abstract class ShinTopBase extends Module{ upCDRIn.io.overCLK := io.clk8x io.dDatOut := downCDROut.io.serDat - io.uDatOut := upCDROut.io.serDat + //override + when( slaveParser.io.isLoop & io.modeSel === false.B){ + upCDRIn.io.serDat := downCDROut.io.serDat + io.dDatOut := false.B + } + + val smUnit = Seq( Module( new SMUnit(depth = 4) ), Module( new SMUnit(depth = 4) ), diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index f1acc7f..c319a48 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -47,6 +47,7 @@ class SlaveParserIO extends Bundle{ val trigAddr = Input( Vec(8, UInt(15.W)) ) val timeStamp = Input(UInt(64.W)) + val isLoop = Output(Bool()) } abstract class SlaveParserBase extends Module{ @@ -169,8 +170,8 @@ abstract class SlaveParserBase extends Module{ - val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) } //子报文负载 - val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) } + val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载 + val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } val isDownRecPing = RegInit(false.B) val isUpRecPing = RegInit(false.B) @@ -620,9 +621,9 @@ trait SlaveParserSync{ this: SlaveParserBase => trait SlaveParserProbe{ this: SlaveParserBase => - val ProbeRecAim = 31.U - val probeRecCnt = RegInit(0.U(5.W)) - val isWatchDogOverflow = probeRecCnt === ProbeRecAim + // val ProbeRecAim = 511.U + val probeRecCnt = RegInit(0.U(9.W)) + val isWatchDogOverflow = probeRecCnt.andR @@ -679,30 +680,20 @@ trait SlaveParserProbe{ this: SlaveParserBase => - io.upOut <> Queue( upSendGen.io.send, 16, true, false ) + io.upOut <> Queue( upSendGen.io.send, 4, true, false ) io.downIn <> downRecParser.io.rec - val tmpFifo = Queue( downSendGen.io.send, 16, true, false ) - when( isLastDevice & ~isReadyToProbe ){ //最后一个设备且不是探测模式 - - upRecParser.io.rec <> tmpFifo //axis短接 + io.downOut <> Queue( downSendGen.io.send, 4, true, false ) + io.upIn <> upRecParser.io.rec - io.downOut.valid := false.B //对外下级io开路 - io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - io.upIn.ready := false.B + io.isLoop := isLastDevice & ~isReadyToProbe - } .otherwise{ - io.downOut <> tmpFifo - io.upIn <> upRecParser.io.rec - - } - - when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~tmpFifo.valid & ~io.upIn.valid ){ + when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){ isLastDevice := isLastDevice_Pending } - when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~tmpFifo.valid & ~io.upIn.valid ){ + when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){ isReadyToProbe := isReadyToProbe_Pending } } diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index 6b00bb2..dfe6e47 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -28,14 +28,7 @@ class SlaveRecParser extends Module{ val STATE_IDLE = 0.U //空闲 val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 - - val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 - - // val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型 - // val STATE_PAYLOAD_ADDR = 3.U //子报文地址 - // val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度 - // val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数 - + val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 val STATE_PAYLOAD_DATA = 3.U //子报文数据 val STATE_CRC = 4.U //CRC校验 val STATE_ERROR = 5.U // @@ -48,10 +41,12 @@ class SlaveRecParser extends Module{ io.isError := stateCurr === STATE_ERROR io.rec.ready := stateCurr =/= STATE_IDLE - crc.io.isEnable := + crc.io.isEnable := io.rec.fire & ( stateCurr === STATE_HEADER | stateCurr === STATE_SUBMSG_HEADER | - stateCurr === STATE_PAYLOAD_DATA + stateCurr === STATE_PAYLOAD_DATA + ) + crc.io.dataIn := io.rec.bits.tdata @@ -60,7 +55,7 @@ class SlaveRecParser extends Module{ val crcData = Reg(UInt(32.W)) val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata ) - when( stateCurr === STATE_CRC ){ + when( io.rec.fire & stateCurr === STATE_CRC ){ crcData := Cat( crcData(23,0), io.rec.bits.tdata ) } diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 3b51d47..59d4d44 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -48,10 +48,12 @@ class SlaveSendGen extends Module{ io.isError := stateCurr === STATE_ERROR - crc.io.isEnable := + crc.io.isEnable := io.send.fire & ( stateCurr === STATE_FRAME_HEADER | stateCurr === STATE_SUBMSG_HEADER | - stateCurr === STATE_SUBMSG_DATA + stateCurr === STATE_SUBMSG_DATA + ) + @@ -84,15 +86,18 @@ class SlaveSendGen extends Module{ val lengthCnt = Reg(UInt(12.W)) val frameLenCnt = Reg(UInt(12.W)) - when( stateCurr === STATE_IDLE || stateCurr === STATE_FRAME_HEADER ){ - frameLenCnt := 0.U - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA ){ - frameLenCnt := frameLenCnt + 1.U + when( io.send.fire ){ + when( stateCurr === STATE_FRAME_HEADER ){ + frameLenCnt := 0.U + } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA ){ + frameLenCnt := frameLenCnt + 1.U + } } - when( stateCurr === STATE_IDLE || stateCurr =/= stateNext ){ + + when( stateCurr =/= stateNext ){ lengthCnt := 0.U - } .otherwise{ + } .elsewhen(io.send.fire){ lengthCnt := lengthCnt + 1.U } @@ -109,32 +114,34 @@ class SlaveSendGen extends Module{ stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), - (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (4-1).U, Mux( + (stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( frameInfo.frameStyle === FRAME_STYLE_COMMON, Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR), STATE_CRC ), - STATE_FRAME_HEADER), - (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), - (stateCurr === STATE_SUBMSG_DATA) -> + STATE_FRAME_HEADER), STATE_FRAME_HEADER ), + (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), + (stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire, Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文 STATE_SUBMSG_DATA - ), - (stateCurr === STATE_CRC) -> Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC), - (stateCurr === STATE_ERROR) -> STATE_IDLE, - // (stateCurr === STATE_WAIT) -> + ), STATE_SUBMSG_DATA ), + (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), + (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), )) - io.data(0).ready := (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U) - io.data(1).ready := (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 1.U) + io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U) + io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 1.U) + + assert( ~(io.data(0).ready & ~io.data(0).valid) ) + assert( ~(io.data(1).ready & ~io.data(1).valid) ) io.send.valid := (stateCurr === STATE_FRAME_HEADER) | (stateCurr === STATE_SUBMSG_HEADER) | - (stateCurr === STATE_SUBMSG_DATA) | + (stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgInfoSel.source === 0.U) | (io.data(1).valid & subMsgInfoSel.source === 1.U) )) | (stateCurr === STATE_CRC) diff --git a/tb/shinTest/ShinTopTb.v b/tb/shinTest/ShinTopTb.v index df92c94..2b6329f 100644 --- a/tb/shinTest/ShinTopTb.v +++ b/tb/shinTest/ShinTopTb.v @@ -453,7 +453,10 @@ initial begin // 顺序索引 - #100000 + #50000 + #50000 + #50000 + begin @@ -508,7 +511,10 @@ initial begin //读写 - #100000 + #50000 + #50000 + #50000 + begin dataBuf[0] = 8'h20;