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高云FPGA：SPI发送前2byte代码规范化修复

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This commit is contained in:
Ruige Lee
2025-02-26 17:27:16 +08:00
parent 9a30c44250
commit b167d3affa
1 changed files with 5 additions and 1 deletions
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6
src/main/scala/backBoard/SpiSlv.scala
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@@ -66,9 +66,12 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
bitSel := 0.U bitSel := 0.U
byteSel := 0.U byteSel := 0.U
cmd_100M := 0.U cmd_100M := 0.U
exReg_100M := upReg(0)
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ //CS为低，且SCK上跳的第0byte } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ //CS为低，且SCK上跳的第0byte
cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) ) cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exReg_100M := upReg(0)
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U ){ when( byteSel === 1.U ){
exReg_100M := upReg(1) exReg_100M := upReg(1)
@@ -83,6 +86,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) ) exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
} }
when( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){ when( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
exMask_100M := Cat( exReg_100M, exMask_100M(7,0) ) exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){ } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){