From b167d3affa513b215326161d774625907e1e8b83 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 26 Feb 2025 17:27:16 +0800 Subject: [PATCH] =?UTF-8?q?=E9=AB=98=E4=BA=91FPGA=EF=BC=9ASPI=E5=8F=91?= =?UTF-8?q?=E9=80=81=E5=89=8D2byte=E4=BB=A3=E7=A0=81=E8=A7=84=E8=8C=83?= =?UTF-8?q?=E5=8C=96=E4=BF=AE=E5=A4=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/SpiSlv.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala index 66c2ceb..62841bf 100644 --- a/src/main/scala/backBoard/SpiSlv.scala +++ b/src/main/scala/backBoard/SpiSlv.scala @@ -66,9 +66,12 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal => bitSel := 0.U byteSel := 0.U cmd_100M := 0.U - exReg_100M := upReg(0) } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ //CS为低，且SCK上跳的第0byte cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) ) + } + + when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 + exReg_100M := upReg(0) } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit when( byteSel === 1.U ){ exReg_100M := upReg(1) @@ -83,6 +86,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal => exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) ) } + when( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){ exMask_100M := Cat( exReg_100M, exMask_100M(7,0) ) } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){