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高云FPGA模块：允许SPI搬运前两byte，有隐患否？

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This commit is contained in:
Ruige Lee
2025-02-26 15:40:18 +08:00
parent ea6ea66040
commit 9a30c44250
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/SpiSlv.scala
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@@ -62,14 +62,14 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
bitSel := 0.U
byteSel := 0.U
cmd_100M := 0.U
exReg_100M := upReg(0)
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ //CS为低，且SCK上跳的第0byte
cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U ){
exReg_100M := upReg(1)
} .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
@@ -79,7 +79,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
} .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
exReg_100M := spiRegDown.io.datar
}
} .elsewhen( isSckPosedge & ~shiftCSn(1) & (byteSel =/= 0.U | byteSel =/= 1.U) ){
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
}