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回滚spi_sel

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RuigeLee
2026-02-06 09:26:20 +08:00
parent 4e32742de8
commit aa25ae5b6a
1 changed files with 2 additions and 0 deletions
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2
src/main/scala/backBoard/shin/MstSlvSwitch.scala
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@@ -24,6 +24,7 @@ class TopBase_IO_Bundle extends Bundle{
val hwSerial = Input(UInt(48.W)) val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W)) val uniCode = Input(UInt(64.W))
val spiSel = Output(UInt(2.W))
} }
@@ -92,6 +93,7 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
io.iSync := interface.io.sync io.iSync := interface.io.sync
io.spiSel := interface.io.cReg.spiSel
val sram = Seq( val sram = Seq(
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },