From aa25ae5b6a57ec9d0b4d886fd009f5be28375aa3 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 6 Feb 2026 09:26:20 +0800 Subject: [PATCH] =?UTF-8?q?=E5=9B=9E=E6=BB=9Aspi=5Fsel?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/MstSlvSwitch.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 7d4312d..52ac6c8 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -24,6 +24,7 @@ class TopBase_IO_Bundle extends Bundle{ val hwSerial = Input(UInt(48.W)) val uniCode = Input(UInt(64.W)) + val spiSel = Output(UInt(2.W)) } @@ -92,6 +93,7 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ io.iSync := interface.io.sync + io.spiSel := interface.io.cReg.spiSel val sram = Seq( for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) }, for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },