diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index 7d4312d..52ac6c8 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -24,6 +24,7 @@ class TopBase_IO_Bundle extends Bundle{
   val hwSerial = Input(UInt(48.W))
   val uniCode = Input(UInt(64.W))
 
+  val spiSel  = Output(UInt(2.W))
 }
 
 
@@ -92,6 +93,7 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
 
   io.iSync := interface.io.sync
 
+  io.spiSel   := interface.io.cReg.spiSel
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },