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高云FPGA:din16默认滤波参数修改

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Ruige Lee
2025-03-12 18:06:05 +08:00
parent 0612a99da2
commit a0799ae62f
1 changed files with 1 additions and 1 deletions
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src/main/scala/backBoard/DIn16.scala
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@@ -11,7 +11,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) )) val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
val flitTrigger = Wire(Vec(9, Bool())) val flitTrigger = Wire(Vec(9, Bool()))
val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) } val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 2.U(8.W) ) }
val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) } val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }