From a0799ae62f11527ddc76569102a1ee377b9c1c37 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 12 Mar 2025 18:06:05 +0800 Subject: [PATCH] =?UTF-8?q?=E9=AB=98=E4=BA=91FPGA:din16=E9=BB=98=E8=AE=A4?= =?UTF-8?q?=E6=BB=A4=E6=B3=A2=E5=8F=82=E6=95=B0=E4=BF=AE=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/DIn16.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/DIn16.scala b/src/main/scala/backBoard/DIn16.scala index d96a992..74421c7 100644 --- a/src/main/scala/backBoard/DIn16.scala +++ b/src/main/scala/backBoard/DIn16.scala @@ -11,7 +11,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal => val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) )) val flitTrigger = Wire(Vec(9, Bool())) - val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) } + val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 2.U(8.W) ) } val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }