diff --git a/src/main/scala/backBoard/DIn16.scala b/src/main/scala/backBoard/DIn16.scala
index d96a992..74421c7 100644
--- a/src/main/scala/backBoard/DIn16.scala
+++ b/src/main/scala/backBoard/DIn16.scala
@@ -11,7 +11,7 @@ trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
 
   val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
   val flitTrigger = Wire(Vec(9, Bool()))
-  val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
+  val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 2.U(8.W) ) }
   val digitalIn     = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }