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RuigeLee
2023-11-07 15:45:31 +08:00
parent 7d8a4851f9
commit 99d3490173
5 changed files with 98 additions and 94 deletions
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12
src/main/scala/Switch/Switch.scala
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@@ -60,15 +60,9 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
val dmaMst = Module(new DmaNode(dma_edge))
dmaMst.io.triTx := outer.dmaReg.module.io.triTx
outer.dmaReg.module.io.triRx := dmaMst.io.triRx
dmaMst.io.sel <> outer.dmaReg.module.io.sel
dmaMst.io.r_TxPtr := outer.dmaReg.module.io.r_TxPtr
dmaMst.io.r_RxPtr := outer.dmaReg.module.io.r_RxPtr
dmaMst.io.r_TxLen := outer.dmaReg.module.io.r_TxLen
outer.dmaReg.module.io.r_RxLen := dmaMst.io.r_RxLen
dmaMst.io.dmaMst.D.bits := dma_bus.d.bits
dmaMst.io.dmaMst.D.valid := dma_bus.d.valid
dma_bus.d.ready := dmaMst.io.dmaMst.D.ready
@@ -146,8 +140,8 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
for( i <- 0 until chn+1 ){
tempTxPort(chn+1-1).valid := false.B
tempTxPort(chn+1-1).bits := 0.U.asTypeOf(new Mac_Stream_Bundle)
tempTxPort(i).valid := false.B
tempTxPort(i).bits := 0.U.asTypeOf(new Mac_Stream_Bundle)
}
robin.io.deq.rx.ready := false.B