diff --git a/src/main/scala/Switch/DMA.scala b/src/main/scala/Switch/DMA.scala index 0a8dee5..d73e29c 100644 --- a/src/main/scala/Switch/DMA.scala +++ b/src/main/scala/Switch/DMA.scala @@ -17,13 +17,7 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{ val dmaMst = new MacTileLinkMasterIO - val triTx = Input ( Vec( chn, Bool()) ) - val triRx = Output( Vec( chn, Bool()) ) - val r_TxPtr = Input(UInt(32.W)) - val r_RxPtr = Input(UInt(32.W)) - val r_TxLen = Input(UInt(16.W)) - val r_RxLen = Output(UInt(16.W)) - + val sel = Vec( chn, Flipped(new DMA_Register_Bundle) ) } @@ -47,13 +41,18 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend val dmaAValid = RegInit(false.B) val dmaABits = Reg(new TLBundleA(edgeOut.bundle)) val dmaAddress = Reg( UInt(32.W) ) + + val trigRxNum = Reg(UInt((log2Ceil(chn)).W)) + val trigTxNum = Reg(UInt((log2Ceil(chn)).W)) + + val rxLength = RegInit(0.U) } trait DMAMstFSM{ this: DMAMstBase => stateNxt := Mux1H(Seq( - ( stateCur === stateIdle ) -> Mux( (io.triTx.foldLeft(false.B)(_|_) & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.valid, stateRx, stateIdle ) ), + ( stateCur === stateIdle ) -> Mux( (0 until chn).map{i => (io.sel(i).triTx & io.sel(i).r_TxLen > 32.U)}.foldLeft(false.B)(_|_) , stateTx, Mux( rxBuff.mInfo.source.valid, stateRx, stateIdle ) ), ( stateCur === stateRx ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ), ( stateCur === stateTx ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ), )) @@ -64,7 +63,7 @@ trait DMAMstFSM{ this: DMAMstBase => } .elsewhen( io.dmaMst.A.fire ){ stateDMA := 2.U } .elsewhen( io.dmaMst.D.fire & isLastD ){ - when( stateCur === stateTx & dmaAddress === (io.r_TxPtr + io.r_TxLen) ){ + when( stateCur === stateTx & dmaAddress === (io.sel(trigTxNum).r_TxPtr + io.sel(trigTxNum).r_TxLen) ){ stateDMA := 0.U } .elsewhen( stateCur === stateRx & ~rxBuff.io.deq.valid ){ stateDMA := 0.U @@ -80,13 +79,28 @@ trait DMAMstTileLink{ this: DMAMstBase => + val mInfoValid = stateCur === stateTx + when( rxBuff.mInfo.source.valid & stateCur === stateIdle & stateNxt === stateRx ){ + assert( rxBuff.mInfo.source.bits(48) === 1.U ) + trigRxNum := rxBuff.mInfo.source.bits + dmaAddress := io.sel(rxBuff.mInfo.source.bits( log2Ceil(chn)-1, 0 )).r_RxPtr + } - when( stateCur === stateIdle & stateNxt === stateTx ){ - dmaAddress := io.r_TxPtr - } .elsewhen( stateCur === stateIdle & stateNxt === stateRx ){ - dmaAddress := io.r_RxPtr - } .elsewhen( io.dmaMst.A.fire ){ + for( i <- 0 until chn ){ + io.sel(i).triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U + io.sel(i).r_RxLen := RegEnable( rxLength + 1.U, io.sel(i).triRx ) + } + + for( i <- 0 until chn ){ + when( io.sel(i).triTx & io.sel(i).r_TxLen > 32.U & stateCur === stateIdle ){ + trigTxNum := i.U + dmaAddress := io.sel(i).r_TxPtr + assert( stateNxt === stateTx ) + } + } + + when( io.dmaMst.A.fire ){ dmaAddress := dmaAddress + 1.U } @@ -129,7 +143,7 @@ trait DMAMstTileLink{ this: DMAMstBase => trait DMAMstBuff{ this: DMAMstBase => - val rxLength = RegInit(0.U) + when( rxBuff.io.deq.fire ){ when( rxBuff.io.deq.bits.isStart ){ @@ -139,32 +153,15 @@ trait DMAMstBuff{ this: DMAMstBase => } } - val trigRxNum = Reg(UInt((log2Ceil(chn)).W)) - when( rxBuff.mInfo.source.valid ){ - assert( rxBuff.mInfo.source.bits(48) === 1.U ) - trigRxNum := rxBuff.mInfo.source.bits - } - for( i <- 0 until chn ){ - io.triRx(i) := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast & trigRxNum === i.U - } - - io.r_RxLen := RegEnable( rxLength, io.triRx.foldLeft(false.B)(_|_) ) txBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx txBuff.io.enq.bits.data := io.dmaMst.D.bits.data - txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.r_TxPtr, io.dmaMst.A.fire) - txBuff.io.enq.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen) + txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.sel(trigTxNum).r_TxPtr, io.dmaMst.A.fire) + txBuff.io.enq.bits.isLast := dmaAddress === (io.sel(trigTxNum).r_TxPtr + io.sel(trigTxNum).r_TxLen) - val trigTxNum = Reg(UInt((log2Ceil(chn)).W)) - val mInfoValid = stateCur === stateTx - for( i <- 0 until chn ){ - when( io.triTx(i) & io.r_TxLen(i) > 32.U & stateCur === stateIdle ){ - trigTxNum := i.U - } - } } diff --git a/src/main/scala/Switch/DMARegisters.scala b/src/main/scala/Switch/DMARegisters.scala index d2ce595..d839f66 100644 --- a/src/main/scala/Switch/DMARegisters.scala +++ b/src/main/scala/Switch/DMARegisters.scala @@ -9,17 +9,22 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ + +class DMA_Register_Bundle extends Bundle{ + val r_TxPtr = Output(UInt(32.W)) + val r_RxPtr = Output(UInt(32.W)) + val r_TxLen = Output(UInt(16.W)) + val r_RxLen = Input (UInt(16.W)) + val triTx = Output( Bool()) + val triRx = Input ( Bool()) +} + + class DmaRegIO(implicit p: Parameters) extends SwitchBundle{ val MacAddr = Output(UInt(48.W)) - - val r_TxPtr = Output( Vec(chn, UInt(32.W)) ) - val r_RxPtr = Output( Vec(chn, UInt(32.W)) ) - val r_TxLen = Output( Vec(chn, UInt(16.W)) ) - val r_RxLen = Input ( Vec(chn, UInt(16.W)) ) - val triTx = Output( Vec( chn, Bool()) ) - val triRx = Input ( Vec( chn, Bool()) ) + val sel = Vec( chn, new DMA_Register_Bundle ) } class DmaReg(implicit p: Parameters) extends LazyModule with HasSwitchParameters{ @@ -58,59 +63,67 @@ class DmaRegImp(outer: DmaReg)(implicit p: Parameters) extends LazyModuleImp(out val triRx = for( i <- 0 until chn ) yield { RegInit(false.B) } for( i <- 0 until chn ) { - io.r_TxPtr(i) := txPtr(i) - io.r_RxPtr(i) := rxPtr(i) - io.r_TxLen(i) := txLen(i) + io.sel(i).r_TxPtr := txPtr(i) + io.sel(i).r_RxPtr := rxPtr(i) + io.sel(i).r_TxLen := txLen(i) } - for( i <- 0 until chn ) { when( io.triRx(i) ) { triRx(i) := true.B } } + for( i <- 0 until chn ) { when( io.sel(i).triRx ) { triRx(i) := true.B } } - outer.configNode.regmap( - ( 0 << 2 ) -> - RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( - RegField(32) - )), + val comMap = Seq( + ( 0 << 2 ) -> + RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq( + RegField(32) + )), - ( 1 << 2 ) -> - RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( - RegField(32) - )), + ( 1 << 2 ) -> + RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq( + RegField(32) + )) + ) + + val trigMap = + ((0 until chn).map{ i => + ( (10*i + 10) << 2 ) -> + RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq( + RegField.w(1, RegWriteFn((valid, data) => { io.sel(i).triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))), + RegField(1, triRx(i), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))) + )) + }) + + val lenMap = + (0 until chn).map{ i => + ( (10*i + 11) << 2 ) -> + RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq( + RegField(16, txLen(i), RegFieldDesc("txLen", "length of tx", reset=Some(65535))), + RegField.r(16, io.sel(i).r_RxLen, RegFieldDesc("rxLen", "length of rx")), + )) + } + + val txAddrMap = + (0 until chn).map{ i => + ( (10*i + 12) << 2 ) -> + RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq( + RegField(32, txPtr(i), RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))), + )) + } + + val rxAddrMap = + (0 until chn).map{ i => + ( (10*i + 13) << 2 ) -> + RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq( + RegField(32, rxPtr(i), RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))), + )) + } - // (0 until chn).map{ i => - // ( (10*i + 10) << 2 ) -> - // RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq( - // RegField.w(1, RegWriteFn((valid, data) => { io.triTx(i) := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))), - // RegField(1, triRx(i), RegFieldDesc("bd", s"bd$i", reset=Some(0x0))) - // )) - // } + val regMap = comMap ++ trigMap ++ lenMap ++ txAddrMap ++ rxAddrMap + outer.configNode.regmap(regMap: _*) - // (0 until chn).map{ i => - // ( (10*i + 11) << 2 ) -> - // RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq( - // RegField(16, txLen(i), RegFieldDesc("txLen", "length of tx", reset=Some(65535))), - // RegField.r(16, io.r_RxLen(i), RegFieldDesc("rxLen", "length of rx")), - // )) - // } - // (0 until chn).map{ i => - // ( (10*i + 12) << 2 ) -> - // RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq( - // RegField(32, txPtr(i), RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))), - // )) - // } - - // (0 until chn).map{ i => - // ( (10*i + 13) << 2 ) -> - // RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq( - // RegField(32, rxPtr(i), RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))), - // )) - // } - - ) diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala index 1bcf821..32df354 100644 --- a/src/main/scala/Switch/MacRegisters.scala +++ b/src/main/scala/Switch/MacRegisters.scala @@ -66,7 +66,7 @@ class MacReg(chn: Int)(implicit p: Parameters) extends LazyModule{ // DTS - val dtsdevice = new SimpleDevice(s"mac($chn)",Seq(s"mac_($chn)")) + val dtsdevice = new SimpleDevice(s"mac$chn",Seq(s"mac_$chn")) val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int)) diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala index bf597d3..9f8d9c2 100644 --- a/src/main/scala/Switch/Switch.scala +++ b/src/main/scala/Switch/Switch.scala @@ -60,15 +60,9 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out val dmaMst = Module(new DmaNode(dma_edge)) - dmaMst.io.triTx := outer.dmaReg.module.io.triTx - outer.dmaReg.module.io.triRx := dmaMst.io.triRx + dmaMst.io.sel <> outer.dmaReg.module.io.sel - dmaMst.io.r_TxPtr := outer.dmaReg.module.io.r_TxPtr - dmaMst.io.r_RxPtr := outer.dmaReg.module.io.r_RxPtr - dmaMst.io.r_TxLen := outer.dmaReg.module.io.r_TxLen - outer.dmaReg.module.io.r_RxLen := dmaMst.io.r_RxLen - dmaMst.io.dmaMst.D.bits := dma_bus.d.bits dmaMst.io.dmaMst.D.valid := dma_bus.d.valid dma_bus.d.ready := dmaMst.io.dmaMst.D.ready @@ -146,8 +140,8 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out for( i <- 0 until chn+1 ){ - tempTxPort(chn+1-1).valid := false.B - tempTxPort(chn+1-1).bits := 0.U.asTypeOf(new Mac_Stream_Bundle) + tempTxPort(i).valid := false.B + tempTxPort(i).bits := 0.U.asTypeOf(new Mac_Stream_Bundle) } robin.io.deq.rx.ready := false.B diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala index 26cdca8..bf30930 100644 --- a/src/main/scala/Switch/WithSwitch.scala +++ b/src/main/scala/Switch/WithSwitch.scala @@ -16,7 +16,7 @@ trait WithSwitchMix { this: BaseSubsystem => // pbus.coupleTo("switch_cfg") { switch0.tlMasterNode := TLFragmenter(pbus) := _ } for( i <- 0 until 3 ){ - pbus.coupleTo("switch_cfg") { switch.macReg(i).configNode := TLFragmenter(pbus) := _ } + pbus.coupleTo("switch_cfg") { switch.macReg(i).configNode := TLFragmenter(pbus) := _ } ibus.fromSync := switch.macReg(i).int_node }