164 lines
4.1 KiB
Scala
164 lines
4.1 KiB
Scala
package Switch
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import chisel3._
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import chisel3.util._
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import MAC._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import chisel3.experimental.dataview._
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class SwitchIO(implicit p: Parameters) extends SwitchBundle{
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val mii = Vec( chn, new MII )
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val isLoopBack = Output(Vec( chn, Bool()))
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val asyncReset = Input(AsyncReset())
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}
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class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
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val tlClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
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Seq(TLMasterParameters.v1(
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name = "DMA",
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sourceId = IdRange(0, chn),
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))
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)))
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val macReg = for( i <- 0 until chn ) yield { LazyModule(new MacReg(i)) }
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val dmaReg = LazyModule(new DmaReg)
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lazy val module = new SwitchImp(this)
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}
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class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
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val io = IO(new SwitchIO)
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val ( dma_bus, dma_edge ) = outer.tlClientNode.out.head
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val mac = ( 0 until chn ).map{ i =>
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Module(new MacNode)
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}
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( 0 until chn ).map{ i =>
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mac(i).io.mii <> io.mii(i)
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mac(i).io.asyncReset := io.asyncReset
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io.isLoopBack(i) := mac(i).io.isLoopBack
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outer.macReg(i).module.io.asyncReset := io.asyncReset
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outer.macReg(i).module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(i).io.cfg
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}
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val dmaMst = Module(new DmaNode(dma_edge))
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dmaMst.io.sel <> outer.dmaReg.module.io.sel
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dmaMst.io.dmaMst.D.bits := dma_bus.d.bits
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dmaMst.io.dmaMst.D.valid := dma_bus.d.valid
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dma_bus.d.ready := dmaMst.io.dmaMst.D.ready
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dma_bus.a.valid := dmaMst.io.dmaMst.A.valid
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dma_bus.a.bits := dmaMst.io.dmaMst.A.bits
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dmaMst.io.dmaMst.A.ready := dma_bus.a.ready
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val robin = Module(new Robin)
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// dmaMst.ex.tx <>
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// <> mac(0).ex.tx
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for( i <- 0 until chn ){
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mac(i).ex.rx <> robin.io.enq(i).rx
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mac(i).ex.mInfo <> robin.io.enq(i).mInfo
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}
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dmaMst.ex.rx <> robin.io.enq(chn+1-1).rx
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dmaMst.ex.mInfo <> robin.io.enq(chn+1-1).mInfo
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val destTable = Wire( Vec( chn+1, Vec( 4, UInt(48.W) ) ) )
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for( i <- 0 until chn+1 ){
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destTable(i)(0) := "h102030405A00".U + i.U
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destTable(i)(1) := "h102030405B00".U + i.U
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destTable(i)(2) := "h102030405C00".U + i.U
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destTable(i)(3) := "h102030405D00".U + i.U
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}
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val isHit = Reg(Bool())
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val destChn = Reg(UInt((log2Ceil(chn+1)).W))
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val isMuxBusy = RegInit(false.B)
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when( robin.io.deq.rx.fire & robin.io.deq.rx.bits.isLast ){
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assert( isMuxBusy )
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isMuxBusy := false.B
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} .elsewhen( robin.io.deq.mInfo.dest.valid ){
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assert( ~isMuxBusy )
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isMuxBusy := true.B
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isHit := false.B
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for( i <- 0 until chn+1 ){
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when(
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robin.io.deq.mInfo.dest.bits === destTable(i)(0) ||
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robin.io.deq.mInfo.dest.bits === destTable(i)(1) ||
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robin.io.deq.mInfo.dest.bits === destTable(i)(2) ||
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robin.io.deq.mInfo.dest.bits === destTable(i)(3)
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){
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isHit := true.B
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destChn := i.U
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}
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}
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}
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val tempTxPort = Wire( Vec( chn+1, Decoupled(new Mac_Stream_Bundle) ) )
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for( i <- 0 until chn ){
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mac(i).ex.tx.valid := tempTxPort(i).valid
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mac(i).ex.tx.bits := tempTxPort(i).bits
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tempTxPort(i).ready := mac(i).ex.tx.ready
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}
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dmaMst.ex.tx.valid := tempTxPort(chn+1-1).valid
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dmaMst.ex.tx.bits := tempTxPort(chn+1-1).bits
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tempTxPort(chn+1-1).ready := dmaMst.ex.tx.ready
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val allTxReady = tempTxPort.map{ x => x.ready }.foldLeft(true.B)(_&_)
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for( i <- 0 until chn+1 ){
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tempTxPort(i).valid := false.B
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tempTxPort(i).bits := 0.U.asTypeOf(new Mac_Stream_Bundle)
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}
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robin.io.deq.rx.ready := false.B
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when( isMuxBusy ){
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when( isHit ){
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tempTxPort(destChn).valid := robin.io.deq.rx.valid
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tempTxPort(destChn).bits := robin.io.deq.rx.bits
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robin.io.deq.rx.ready := tempTxPort(destChn).ready
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} .otherwise{
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for( i <- 0 until chn+1 ){
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tempTxPort(i).valid := robin.io.deq.rx.valid & allTxReady
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tempTxPort(i).bits := robin.io.deq.rx.bits
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}
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robin.io.deq.rx.ready := allTxReady
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}
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}
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}
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