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修复CDRIn的异步复位

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RuigeLee
2025-09-11 18:56:13 +08:00
parent f42c9044d8
commit 99b9d9a72f
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/backBoard/shin/CDRIn.scala
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@@ -24,11 +24,11 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
dontTouch(sampleReg)
for( i <- 0 until clkNum ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
}
val sampleReg_sync = for( i <- 0 until clkNum ) yield {
ShiftRegisters(sampleReg(i), 8)
ShiftRegisters(sampleReg(i), 8, false.B, true.B)
}
for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}