From 99b9d9a72f35e105f9be7e4312e3c543e8e10fb2 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 11 Sep 2025 18:56:13 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8DCDRIn=E7=9A=84=E5=BC=82?= =?UTF-8?q?=E6=AD=A5=E5=A4=8D=E4=BD=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/CDRIn.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/shin/CDRIn.scala b/src/main/scala/backBoard/shin/CDRIn.scala index 68f5836..ee91f76 100644 --- a/src/main/scala/backBoard/shin/CDRIn.scala +++ b/src/main/scala/backBoard/shin/CDRIn.scala @@ -24,11 +24,11 @@ class CDRInMultiSample extends Module with RequireAsyncReset{ dontTouch(sampleReg) for( i <- 0 until clkNum ) { - sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) } + sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) } } val sampleReg_sync = for( i <- 0 until clkNum ) yield { - ShiftRegisters(sampleReg(i), 8) + ShiftRegisters(sampleReg(i), 8, false.B, true.B) } for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}