diff --git a/src/main/scala/backBoard/shin/CDRIn.scala b/src/main/scala/backBoard/shin/CDRIn.scala
index 68f5836..ee91f76 100644
--- a/src/main/scala/backBoard/shin/CDRIn.scala
+++ b/src/main/scala/backBoard/shin/CDRIn.scala
@@ -24,11 +24,11 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
   dontTouch(sampleReg)
   
   for( i <- 0 until clkNum ) {
-    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
+    sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asAsyncReset){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
   }
 
   val sampleReg_sync = for( i <- 0 until clkNum ) yield {
-    ShiftRegisters(sampleReg(i), 8)
+    ShiftRegisters(sampleReg(i), 8, false.B, true.B)
   }
   for( i <- 0 until clkNum; j <- 0 until 8 ){dontTouch(sampleReg_sync(i)(j))}