顶层时钟更新

src/main/verilog/backBoardMstTop.v

@@ -47,7 +47,7 @@ wire       reset_calib;
 wire lock_o;
 wire       reset_stop;
 
-always@(posedge clk_10m_a) begin
+always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end

src/main/verilog/di16_top.v

@@ -46,7 +46,7 @@ end
 
 assign resetn = resetCnt == 4'd15;
 
-always@(posedge clk_10m_a) begin
+always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end

src/main/verilog/do16_top.v

@@ -52,7 +52,7 @@ end
 
 assign resetn = resetCnt == 4'd15;
 
-always@(posedge clk_10m_a) begin
+always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end