From 99525c4f015697e669678542b72a36976810c638 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Thu, 23 May 2024 13:41:18 +0800 Subject: [PATCH] =?UTF-8?q?=E9=A1=B6=E5=B1=82=E6=97=B6=E9=92=9F=E6=9B=B4?= =?UTF-8?q?=E6=96=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/verilog/backBoardMstTop.v | 2 +- src/main/verilog/di16_top.v | 2 +- src/main/verilog/do16_top.v | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v index e67dda7..56514ae 100644 --- a/src/main/verilog/backBoardMstTop.v +++ b/src/main/verilog/backBoardMstTop.v @@ -47,7 +47,7 @@ wire reset_calib; wire lock_o; wire reset_stop; -always@(posedge clk_10m_a) begin +always@(posedge clock) begin rstn_d <= resetn; rst_n <= rstn_d; end diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v index fea6d09..633fdf7 100644 --- a/src/main/verilog/di16_top.v +++ b/src/main/verilog/di16_top.v @@ -46,7 +46,7 @@ end assign resetn = resetCnt == 4'd15; -always@(posedge clk_10m_a) begin +always@(posedge clock) begin rstn_d <= resetn; rst_n <= rstn_d; end diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v index fd6e200..42d2747 100644 --- a/src/main/verilog/do16_top.v +++ b/src/main/verilog/do16_top.v @@ -52,7 +52,7 @@ end assign resetn = resetCnt == 4'd15; -always@(posedge clk_10m_a) begin +always@(posedge clock) begin rstn_d <= resetn; rst_n <= rstn_d; end