diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v
index e67dda7..56514ae 100644
--- a/src/main/verilog/backBoardMstTop.v
+++ b/src/main/verilog/backBoardMstTop.v
@@ -47,7 +47,7 @@ wire       reset_calib;
 wire lock_o;
 wire       reset_stop;
 
-always@(posedge clk_10m_a) begin
+always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end
diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v
index fea6d09..633fdf7 100644
--- a/src/main/verilog/di16_top.v
+++ b/src/main/verilog/di16_top.v
@@ -46,7 +46,7 @@ end
 
 assign resetn = resetCnt == 4'd15;
 
-always@(posedge clk_10m_a) begin
+always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end
diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v
index fd6e200..42d2747 100644
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -52,7 +52,7 @@ end
 
 assign resetn = resetCnt == 4'd15;
 
-always@(posedge clk_10m_a) begin
+always@(posedge clock) begin
   rstn_d <= resetn;
 	rst_n <= rstn_d;
 end