bug修复：定义CDR清中断和中断到来同时发生的行为

src/main/scala/backBoard/ebus/RoCC2CDR.scala

@@ -414,10 +414,8 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
 
   val interruptReg = RegInit(0.U(32.W))
 
-  when( isTLClearInterrupt ){
-    interruptReg := interruptReg & ~wdata
-  } .otherwise{
-    interruptReg := interruptReg | Cat(
+  when(true.B){
+    interruptReg := (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat(
       intTxEnd(1), intTxEnd(0),
       intRxError(1), intRxError(0),
       intRxStart(1), intRxStart(0),
@@ -428,6 +426,8 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
   }
 
 
+
+
   io.interrupt :=  
     intTxEnd(0) |
     intTxEnd(1) |