From 9937485831fa66bda8f22fbf41f8d2cc05db20f7 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 27 Feb 2025 17:27:15 +0800
Subject: [PATCH] =?UTF-8?q?bug=E4=BF=AE=E5=A4=8D=EF=BC=9A=E5=AE=9A?=
 =?UTF-8?q?=E4=B9=89CDR=E6=B8=85=E4=B8=AD=E6=96=AD=E5=92=8C=E4=B8=AD?=
 =?UTF-8?q?=E6=96=AD=E5=88=B0=E6=9D=A5=E5=90=8C=E6=97=B6=E5=8F=91=E7=94=9F?=
 =?UTF-8?q?=E7=9A=84=E8=A1=8C=E4=B8=BA?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/ebus/RoCC2CDR.scala | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
index 7733364..894926a 100644
--- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala
+++ b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
@@ -414,20 +414,20 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
 
   val interruptReg = RegInit(0.U(32.W))
 
-  when( isTLClearInterrupt ){
-    interruptReg := interruptReg & ~wdata
-  } .otherwise{
-    interruptReg := interruptReg | Cat(
+  when(true.B){
+    interruptReg := (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat(
       intTxEnd(1), intTxEnd(0),
       intRxError(1), intRxError(0),
       intRxStart(1), intRxStart(0),
       intRxEnd(1), intRxEnd(0),
       intTxFifoDeq(1), intTxFifoDeq(0),
       intRxFifoEnq(1), intRxFifoEnq(0)
-    )
+    )    
   }
 
 
+
+
   io.interrupt :=  
     intTxEnd(0) |
     intTxEnd(1) |