diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
index 7733364..894926a 100644
--- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala
+++ b/src/main/scala/backBoard/ebus/RoCC2CDR.scala
@@ -414,20 +414,20 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
 
   val interruptReg = RegInit(0.U(32.W))
 
-  when( isTLClearInterrupt ){
-    interruptReg := interruptReg & ~wdata
-  } .otherwise{
-    interruptReg := interruptReg | Cat(
+  when(true.B){
+    interruptReg := (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat(
       intTxEnd(1), intTxEnd(0),
       intRxError(1), intRxError(0),
       intRxStart(1), intRxStart(0),
       intRxEnd(1), intRxEnd(0),
       intTxFifoDeq(1), intTxFifoDeq(0),
       intRxFifoEnq(1), intRxFifoEnq(0)
-    )
+    )    
   }
 
 
+
+
   io.interrupt :=  
     intTxEnd(0) |
     intTxEnd(1) |