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bug修复：定义CDR清中断和中断到来同时发生的行为

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This commit is contained in:
Ruige Lee
2025-02-27 17:27:15 +08:00
parent 983b0337c3
commit 9937485831
1 changed files with 5 additions and 5 deletions
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10
src/main/scala/backBoard/ebus/RoCC2CDR.scala
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@@ -414,20 +414,20 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
val interruptReg = RegInit(0.U(32.W)) val interruptReg = RegInit(0.U(32.W))
when( isTLClearInterrupt ){ when(true.B){
interruptReg := interruptReg & ~wdata interruptReg := (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat(
} .otherwise{
interruptReg := interruptReg | Cat(
intTxEnd(1), intTxEnd(0), intTxEnd(1), intTxEnd(0),
intRxError(1), intRxError(0), intRxError(1), intRxError(0),
intRxStart(1), intRxStart(0), intRxStart(1), intRxStart(0),
intRxEnd(1), intRxEnd(0), intRxEnd(1), intRxEnd(0),
intTxFifoDeq(1), intTxFifoDeq(0), intTxFifoDeq(1), intTxFifoDeq(0),
intRxFifoEnq(1), intRxFifoEnq(0) intRxFifoEnq(1), intRxFifoEnq(0)
) )
} }
io.interrupt := io.interrupt :=
intTxEnd(0) | intTxEnd(0) |
intTxEnd(1) | intTxEnd(1) |