跨时钟域有严重设计缺陷

2023-07-06 22:11:49 +08:00
parent 78a2f4ba47
commit 9322f63bc5
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/mac/MAC.scala
+++ b/src/main/scala/mac/MAC.scala
@@ -655,7 +655,7 @@ val rxethmac = Module(new MacRx)
    val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)

    Transmitting := ~r_FullD & WillTransmit_q
-    RxEnSync := RegEnable(r_RxEn, false.B, ~io.mrxdv_pad_i)
+    RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mrxdv_pad_i)
  }