带主机联调，slv1还没更新索引

src/main/scala/backBoard/shin/MasterParser.scala

@@ -32,26 +32,34 @@ class MasterParserIO extends Bundle{
 abstract class MasterParserBase extends Module{
   val io: MasterParserIO = IO(new MasterParserIO)
 
-  val txCnt = Reg(UInt(11.W))
+  val txCnt = Reg(UInt(12.W))
   val txLen = Reg(UInt(11.W))
   val txAddr = Reg(UInt(15.W))
 
-  val rxCnt = Reg(UInt(11.W))
+  val rxCnt = Reg(UInt(12.W))
+  val rxLen = Reg(UInt(11.W))
   val rxAddr = Reg(UInt(15.W))
 
   val reqReady = RegInit(true.B)
 
 
+  val txcrc = Module(new crc32_8)
+  val rxcrc = Module(new crc32_8)
+
+
+
+
   // io.req.ready := reqReady
 
   when( io.req.fire ){
     reqReady := false.B
-  } .elsewhen( io.downOut.fire & txCnt === txLen ){
+  } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
     reqReady := true.B
   }
 
   when( io.req.fire ){
     txLen  := io.req.bits.length
+    rxLen  := io.req.bits.length
     txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
     txCnt := txCnt + 1.U
@@ -77,13 +85,19 @@ abstract class MasterParserBase extends Module{
   io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
-  io.downOut.bits.tdata := io.sram_r.datar
+  io.downOut.bits.tdata := Mux1H(Seq(
+    ( txCnt  <  txLen       ) -> io.sram_r.datar,
+    ( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24),
+    ( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16),
+    ( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8),
+    ( txCnt === txLen + 3.U ) -> txcrc.io.crc( 7, 0),
+  ))
   io.downOut.bits.tuser := false.B 
-  io.downOut.bits.tlast := txCnt === txLen
-
+  io.downOut.bits.tlast := txCnt === (txLen + 3.U)
 
 
 
+  val recCrcCheck = Reg(UInt(32.W))
 
   when( io.req.fire ){
     rxCnt := 0.U
@@ -100,7 +114,7 @@ abstract class MasterParserBase extends Module{
 
 
   io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
-  io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
+  io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc
   io.rsp.bits.length  := rxCnt + 1.U
 
 
@@ -110,6 +124,30 @@ abstract class MasterParserBase extends Module{
 
 
 
+
+  txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
+  txcrc.io.dataIn   := io.downOut.bits.tdata
+  txcrc.reset := reset.asBool | reqReady
+
+  rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen
+  rxcrc.io.dataIn   := io.upIn.bits.tdata
+  rxcrc.reset := reset.asBool | io.rsp.fire
+
+
+
+  when( io.upIn.fire ){
+    when( rxCnt === rxLen ){
+      recCrcCheck := io.upIn.bits.tdata << 24
+    } .elsewhen( rxCnt === (rxLen + 1.U) ){
+      recCrcCheck := Cat( recCrcCheck(31,24), io.upIn.bits.tdata, recCrcCheck(15,0) )
+    } .elsewhen( rxCnt === (rxLen + 2.U) ){
+      recCrcCheck := Cat( recCrcCheck(31,16), io.upIn.bits.tdata, recCrcCheck( 7,0) )
+    } .elsewhen( rxCnt === (rxLen + 3.U) ){
+      recCrcCheck := Cat( recCrcCheck(31,8), io.upIn.bits.tdata )
+    }
+  }
+
+
 }
 
 

src/main/scala/backBoard/shin/ShinTop.scala

@@ -214,8 +214,8 @@ abstract class ShinTopBase extends Module{
 trait ShinTopMaster{ this: ShinTopBase =>
 
   when(io.modeSel === true.B ){
-    slaveParser.io.downOut <> io.downOut
-    slaveParser.io.upIn    <> io.upIn 
+    masterParser.io.downOut <> io.downOut
+    masterParser.io.upIn    <> io.upIn 
   }
 
   when( io.modeSel === true.B ){

src/main/scala/backBoard/shin/SlaveRecParser.scala

@@ -57,10 +57,10 @@ class SlaveRecParser extends Module{
   crc.reset := reset.asBool | stateCurr === STATE_IDLE
 
   val crcData = Reg(UInt(32.W))
-  val isCrcPass = crc.io.crc === Cat( crcData << 8, io.rec.bits.tdata )
+  val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
 
   when( stateCurr === STATE_CRC ){
-    crcData := Cat( crcData << 8, io.rec.bits.tdata )
+    crcData := Cat( crcData(23,0), io.rec.bits.tdata )
   }
 
   val FRAME_STYLE_COMMON = 0.U

src/main/scala/backBoard/shin/SlaveSendGen.scala

@@ -107,7 +107,7 @@ class SlaveSendGen extends Module{
 
   stateNext := Mux1H(Seq(
     (stateCurr === STATE_IDLE)          -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
-    (stateCurr === STATE_FRAME_HEADER)  -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER),
+    (stateCurr === STATE_FRAME_HEADER)  -> Mux( lengthCnt === (4-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER),
     (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER),
     (stateCurr === STATE_SUBMSG_DATA)   ->
       Mux( lengthCnt === subMsgInfoSel.length-1.U,    //已经发送完成该子报文
@@ -135,6 +135,8 @@ class SlaveSendGen extends Module{
   val tdata_frame_header = Mux1H(Seq(
     (lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4),
     (lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle),
+    (lengthCnt === 2.U) -> frameInfo.frameInfo(15,8),
+    (lengthCnt === 3.U) -> frameInfo.frameInfo( 7,0),
   ))
 
   val tdata_submsg_header = Mux1H(Seq(