diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index f4f7a17..16ab85e 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -32,26 +32,34 @@ class MasterParserIO extends Bundle{ abstract class MasterParserBase extends Module{ val io: MasterParserIO = IO(new MasterParserIO) - val txCnt = Reg(UInt(11.W)) + val txCnt = Reg(UInt(12.W)) val txLen = Reg(UInt(11.W)) val txAddr = Reg(UInt(15.W)) - val rxCnt = Reg(UInt(11.W)) + val rxCnt = Reg(UInt(12.W)) + val rxLen = Reg(UInt(11.W)) val rxAddr = Reg(UInt(15.W)) val reqReady = RegInit(true.B) + val txcrc = Module(new crc32_8) + val rxcrc = Module(new crc32_8) + + + + // io.req.ready := reqReady when( io.req.fire ){ reqReady := false.B - } .elsewhen( io.downOut.fire & txCnt === txLen ){ + } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){ reqReady := true.B } when( io.req.fire ){ txLen := io.req.bits.length + rxLen := io.req.bits.length txCnt := 0.U } .elsewhen( io.downOut.fire ){ txCnt := txCnt + 1.U @@ -77,13 +85,19 @@ abstract class MasterParserBase extends Module{ io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U ) io.downOut.valid := ~reqReady - io.downOut.bits.tdata := io.sram_r.datar + io.downOut.bits.tdata := Mux1H(Seq( + ( txCnt < txLen ) -> io.sram_r.datar, + ( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24), + ( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16), + ( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8), + ( txCnt === txLen + 3.U ) -> txcrc.io.crc( 7, 0), + )) io.downOut.bits.tuser := false.B - io.downOut.bits.tlast := txCnt === txLen - + io.downOut.bits.tlast := txCnt === (txLen + 3.U) + val recCrcCheck = Reg(UInt(32.W)) when( io.req.fire ){ rxCnt := 0.U @@ -100,7 +114,7 @@ abstract class MasterParserBase extends Module{ io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast - io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser + io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc io.rsp.bits.length := rxCnt + 1.U @@ -110,6 +124,30 @@ abstract class MasterParserBase extends Module{ + + txcrc.io.isEnable := io.downOut.fire & txCnt < txLen + txcrc.io.dataIn := io.downOut.bits.tdata + txcrc.reset := reset.asBool | reqReady + + rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen + rxcrc.io.dataIn := io.upIn.bits.tdata + rxcrc.reset := reset.asBool | io.rsp.fire + + + + when( io.upIn.fire ){ + when( rxCnt === rxLen ){ + recCrcCheck := io.upIn.bits.tdata << 24 + } .elsewhen( rxCnt === (rxLen + 1.U) ){ + recCrcCheck := Cat( recCrcCheck(31,24), io.upIn.bits.tdata, recCrcCheck(15,0) ) + } .elsewhen( rxCnt === (rxLen + 2.U) ){ + recCrcCheck := Cat( recCrcCheck(31,16), io.upIn.bits.tdata, recCrcCheck( 7,0) ) + } .elsewhen( rxCnt === (rxLen + 3.U) ){ + recCrcCheck := Cat( recCrcCheck(31,8), io.upIn.bits.tdata ) + } + } + + } diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 6244569..45a6b91 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -214,8 +214,8 @@ abstract class ShinTopBase extends Module{ trait ShinTopMaster{ this: ShinTopBase => when(io.modeSel === true.B ){ - slaveParser.io.downOut <> io.downOut - slaveParser.io.upIn <> io.upIn + masterParser.io.downOut <> io.downOut + masterParser.io.upIn <> io.upIn } when( io.modeSel === true.B ){ diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index b798de9..1edf61c 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -57,10 +57,10 @@ class SlaveRecParser extends Module{ crc.reset := reset.asBool | stateCurr === STATE_IDLE val crcData = Reg(UInt(32.W)) - val isCrcPass = crc.io.crc === Cat( crcData << 8, io.rec.bits.tdata ) + val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata ) when( stateCurr === STATE_CRC ){ - crcData := Cat( crcData << 8, io.rec.bits.tdata ) + crcData := Cat( crcData(23,0), io.rec.bits.tdata ) } val FRAME_STYLE_COMMON = 0.U diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 668f2bb..f9771b4 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -107,7 +107,7 @@ class SlaveSendGen extends Module{ stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), - (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER), + (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (4-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER), (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), (stateCurr === STATE_SUBMSG_DATA) -> Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 @@ -135,6 +135,8 @@ class SlaveSendGen extends Module{ val tdata_frame_header = Mux1H(Seq( (lengthCnt === 0.U) -> frameInfo.frameLenAim(11,4), (lengthCnt === 1.U) -> Cat( frameInfo.frameLenAim(3,0), 0.U(2.W), frameInfo.frameStyle), + (lengthCnt === 2.U) -> frameInfo.frameInfo(15,8), + (lengthCnt === 3.U) -> frameInfo.frameInfo( 7,0), )) val tdata_submsg_header = Mux1H(Seq( diff --git a/tb/shinTest/ShinTopTb.v b/tb/shinTest/ShinTopTb.v index 069afec..7e82eda 100644 --- a/tb/shinTest/ShinTopTb.v +++ b/tb/shinTest/ShinTopTb.v @@ -10,65 +10,346 @@ module ShinTopTb( -wire io_downIn_ready; -reg io_downIn_valid = 0; -reg [7:0] io_downIn_bits_tdata = 0; -reg io_downIn_bits_tlast = 0; -reg io_downIn_bits_tuser = 0; - -reg io_downOut_ready = 1; -wire io_downOut_valid; -wire [7:0] io_downOut_bits_tdata; -wire io_downOut_bits_tlast; -wire io_downOut_bits_tuser; - -wire io_upIn_ready; -reg io_upIn_valid = 0; -reg [7:0] io_upIn_bits_tdata = 0; -reg io_upIn_bits_tlast = 0; -reg io_upIn_bits_tuser = 0; - -reg io_upOut_ready = 1; -wire io_upOut_valid; -wire [7:0] io_upOut_bits_tdata; -wire io_upOut_bits_tlast; -wire io_upOut_bits_tuser; + wire [3:0] io_down_ready; + wire [3:0] io_down_valid; + wire [31:0] io_down_bits_tdata; + wire [3:0] io_down_bits_tlast; + wire [3:0] io_down_bits_tuser; -reg [63:0] timeStamp = 0; + wire [3:0] io_up_ready; + wire [3:0] io_up_valid; + wire [31:0] io_up_bits_tdata; + wire [3:0] io_up_bits_tlast; + wire [3:0] io_up_bits_tuser; + reg [63:0] timeStamp = 0; + reg [10:0] sram_w_0_addrw; + reg [7:0] sram_w_0_dataw; + reg sram_w_0_enw = 1'b0; + reg txCmf = 1'b0; + reg req_valid = 1'b0; + reg [14:0] req_bits_txAddr; + reg [14:0] req_bits_rxAddr; + reg [11:0] req_bits_length; - - - -ShinTop s_ShinTop( +ShinTop s_ShinTop_Mst( .clock(clock), .reset(reset), - .io_downIn_ready(io_downIn_ready), - .io_downIn_valid(io_downIn_valid), - .io_downIn_bits_tdata(io_downIn_bits_tdata), - .io_downIn_bits_tlast(io_downIn_bits_tlast), - .io_downIn_bits_tuser(io_downIn_bits_tuser), - .io_downOut_ready(io_downOut_ready), - .io_downOut_valid(io_downOut_valid), - .io_downOut_bits_tdata(io_downOut_bits_tdata), - .io_downOut_bits_tlast(io_downOut_bits_tlast), - .io_downOut_bits_tuser(io_downOut_bits_tuser), - .io_upIn_ready(io_upIn_ready), - .io_upIn_valid(io_upIn_valid), - .io_upIn_bits_tdata(io_upIn_bits_tdata), - .io_upIn_bits_tlast(io_upIn_bits_tlast), - .io_upIn_bits_tuser(io_upIn_bits_tuser), - .io_upOut_ready(io_upOut_ready), - .io_upOut_valid(io_upOut_valid), - .io_upOut_bits_tdata(io_upOut_bits_tdata), - .io_upOut_bits_tlast(io_upOut_bits_tlast), - .io_upOut_bits_tuser(io_upOut_bits_tuser), + .io_downIn_ready (), + .io_downIn_valid (1'b0), + .io_downIn_bits_tdata (8'd0), + .io_downIn_bits_tlast (1'b0), + .io_downIn_bits_tuser (1'b0), + .io_downOut_ready (io_down_ready[0]), + .io_downOut_valid (io_down_valid[0]), + .io_downOut_bits_tdata(io_down_bits_tdata[7:0]), + .io_downOut_bits_tlast(io_down_bits_tlast[0]), + .io_downOut_bits_tuser(io_down_bits_tuser[0]), + .io_upIn_ready (io_up_ready[0]), + .io_upIn_valid (io_up_valid[0]), + .io_upIn_bits_tdata (io_up_bits_tdata[7:0]), + .io_upIn_bits_tlast (io_up_bits_tlast[0]), + .io_upIn_bits_tuser (io_up_bits_tuser[0]), + .io_upOut_ready (1'b1), + .io_upOut_valid (), + .io_upOut_bits_tdata (), + .io_upOut_bits_tlast (), + .io_upOut_bits_tuser (), + + .io_timeStamp(timeStamp), + + + .io_dSMdeq_0(1'b0), + .io_dSMdeq_1(1'b0), + .io_dSMdeq_2(1'b0), + .io_dSMdeq_3(1'b0), + .io_uSMenq_0(txCmf), + .io_uSMenq_1(1'b0), + .io_uSMenq_2(1'b0), + .io_uSMenq_3(1'b0), + + .io_sram_w_0_addrw(sram_w_0_addrw), + .io_sram_w_0_dataw(sram_w_0_dataw), + .io_sram_w_0_enw (sram_w_0_enw), + .io_sram_w_1_addrw(11'd0), + .io_sram_w_1_dataw(8'h0), + .io_sram_w_1_enw(1'b0), + .io_sram_w_2_addrw(11'd0), + .io_sram_w_2_dataw(8'h0), + .io_sram_w_2_enw(1'b0), + .io_sram_w_3_addrw(11'd0), + .io_sram_w_3_dataw(8'h0), + .io_sram_w_3_enw(1'b0), + .io_sram_r_0_addrr(11'd0), + .io_sram_r_0_datar(), + .io_sram_r_0_enr(1'b0), + .io_sram_r_1_addrr(11'd0), + .io_sram_r_1_datar(), + .io_sram_r_1_enr(1'b0), + .io_sram_r_2_addrr(11'd0), + .io_sram_r_2_datar(), + .io_sram_r_2_enr(1'b0), + .io_sram_r_3_addrr(11'd0), + .io_sram_r_3_datar(), + .io_sram_r_3_enr(1'b0), + + .io_modeSel(1'b1), //主机模式 + + .io_req_valid (req_valid), + .io_req_bits_txAddr(req_bits_txAddr), + .io_req_bits_rxAddr(req_bits_rxAddr), + .io_req_bits_length(req_bits_length), + .io_rsp_valid(), + .io_rsp_bits_isError(), + .io_rsp_bits_length() +); + +ShinTop s_ShinTop_slv0( + .clock(clock), + .reset(reset), + + .io_downIn_ready (io_down_ready[0]), + .io_downIn_valid (io_down_valid[0]), + .io_downIn_bits_tdata (io_down_bits_tdata[7:0]), + .io_downIn_bits_tlast (io_down_bits_tlast[0]), + .io_downIn_bits_tuser (io_down_bits_tuser[0]), + .io_downOut_ready (io_down_ready[1]), + .io_downOut_valid (io_down_valid[1]), + .io_downOut_bits_tdata(io_down_bits_tdata[15:8]), + .io_downOut_bits_tlast(io_down_bits_tlast[1]), + .io_downOut_bits_tuser(io_down_bits_tuser[1]), + .io_upIn_ready (io_up_ready[1]), + .io_upIn_valid (io_up_valid[1]), + .io_upIn_bits_tdata (io_up_bits_tdata[15:8]), + .io_upIn_bits_tlast (io_up_bits_tlast[1]), + .io_upIn_bits_tuser (io_up_bits_tuser[1]), + .io_upOut_ready (io_up_ready[0]), + .io_upOut_valid (io_up_valid[0]), + .io_upOut_bits_tdata (io_up_bits_tdata[7:0]), + .io_upOut_bits_tlast (io_up_bits_tlast[0]), + .io_upOut_bits_tuser (io_up_bits_tuser[0]), + + .io_timeStamp(timeStamp), + + .io_dSMdeq_0(1'b0), + .io_dSMdeq_1(1'b0), + .io_dSMdeq_2(1'b0), + .io_dSMdeq_3(1'b0), + .io_uSMenq_0(1'b0), + .io_uSMenq_1(1'b0), + .io_uSMenq_2(1'b0), + .io_uSMenq_3(1'b0), + + .io_sram_w_0_addrw(11'd0), + .io_sram_w_0_dataw(8'h0), + .io_sram_w_0_enw(1'b0), + .io_sram_w_1_addrw(11'd0), + .io_sram_w_1_dataw(8'h0), + .io_sram_w_1_enw(1'b0), + .io_sram_w_2_addrw(11'd0), + .io_sram_w_2_dataw(8'h0), + .io_sram_w_2_enw(1'b0), + .io_sram_w_3_addrw(11'd0), + .io_sram_w_3_dataw(8'h0), + .io_sram_w_3_enw(1'b0), + .io_sram_r_0_addrr(11'd0), + .io_sram_r_0_datar(), + .io_sram_r_0_enr(1'b0), + .io_sram_r_1_addrr(11'd0), + .io_sram_r_1_datar(), + .io_sram_r_1_enr(1'b0), + .io_sram_r_2_addrr(11'd0), + .io_sram_r_2_datar(), + .io_sram_r_2_enr(1'b0), + .io_sram_r_3_addrr(11'd0), + .io_sram_r_3_datar(), + .io_sram_r_3_enr(1'b0), + + .io_modeSel(1'b0), + + .io_req_valid(1'b0), + .io_req_bits_txAddr(15'h0), + .io_req_bits_rxAddr(15'h0), + .io_req_bits_length(12'd0), + .io_rsp_valid(), + .io_rsp_bits_isError(), + .io_rsp_bits_length() +); + +ShinTop s_ShinTop_slv1( + .clock(clock), + .reset(reset), + + .io_downIn_ready (io_down_ready[1]), + .io_downIn_valid (io_down_valid[1]), + .io_downIn_bits_tdata (io_down_bits_tdata[15:8]), + .io_downIn_bits_tlast (io_down_bits_tlast[1]), + .io_downIn_bits_tuser (io_down_bits_tuser[1]), + .io_downOut_ready (io_down_ready[2]), + .io_downOut_valid (io_down_valid[2]), + .io_downOut_bits_tdata(io_down_bits_tdata[23:16]), + .io_downOut_bits_tlast(io_down_bits_tlast[2]), + .io_downOut_bits_tuser(io_down_bits_tuser[2]), + .io_upIn_ready (io_up_ready[2]), + .io_upIn_valid (io_up_valid[2]), + .io_upIn_bits_tdata (io_up_bits_tdata[23:16]), + .io_upIn_bits_tlast (io_up_bits_tlast[2]), + .io_upIn_bits_tuser (io_up_bits_tuser[2]), + .io_upOut_ready (io_up_ready[1]), + .io_upOut_valid (io_up_valid[1]), + .io_upOut_bits_tdata (io_up_bits_tdata[15:8]), + .io_upOut_bits_tlast (io_up_bits_tlast[1]), + .io_upOut_bits_tuser (io_up_bits_tuser[1]), + + .io_timeStamp(timeStamp), + + .io_dSMdeq_0(1'b0), + .io_dSMdeq_1(1'b0), + .io_dSMdeq_2(1'b0), + .io_dSMdeq_3(1'b0), + .io_uSMenq_0(1'b0), + .io_uSMenq_1(1'b0), + .io_uSMenq_2(1'b0), + .io_uSMenq_3(1'b0), + + .io_sram_w_0_addrw(11'd0), + .io_sram_w_0_dataw(8'h0), + .io_sram_w_0_enw(1'b0), + .io_sram_w_1_addrw(11'd0), + .io_sram_w_1_dataw(8'h0), + .io_sram_w_1_enw(1'b0), + .io_sram_w_2_addrw(11'd0), + .io_sram_w_2_dataw(8'h0), + .io_sram_w_2_enw(1'b0), + .io_sram_w_3_addrw(11'd0), + .io_sram_w_3_dataw(8'h0), + .io_sram_w_3_enw(1'b0), + .io_sram_r_0_addrr(11'd0), + .io_sram_r_0_datar(), + .io_sram_r_0_enr(1'b0), + .io_sram_r_1_addrr(11'd0), + .io_sram_r_1_datar(), + .io_sram_r_1_enr(1'b0), + .io_sram_r_2_addrr(11'd0), + .io_sram_r_2_datar(), + .io_sram_r_2_enr(1'b0), + .io_sram_r_3_addrr(11'd0), + .io_sram_r_3_datar(), + .io_sram_r_3_enr(1'b0), + + .io_modeSel(1'b0), + + .io_req_valid(1'b0), + .io_req_bits_txAddr(15'h0), + .io_req_bits_rxAddr(15'h0), + .io_req_bits_length(12'd0), + .io_rsp_valid(), + .io_rsp_bits_isError(), + .io_rsp_bits_length() +); + +ShinTop s_ShinTop_slv2( + .clock(clock), + .reset(reset), + + .io_downIn_ready (io_down_ready[2]), + .io_downIn_valid (io_down_valid[2]), + .io_downIn_bits_tdata (io_down_bits_tdata[23:16]), + .io_downIn_bits_tlast (io_down_bits_tlast[2]), + .io_downIn_bits_tuser (io_down_bits_tuser[2]), + .io_downOut_ready (io_down_ready[3]), + .io_downOut_valid (io_down_valid[3]), + .io_downOut_bits_tdata(io_down_bits_tdata[31:24]), + .io_downOut_bits_tlast(io_down_bits_tlast[3]), + .io_downOut_bits_tuser(io_down_bits_tuser[3]), + .io_upIn_ready (io_up_ready[3]), + .io_upIn_valid (io_up_valid[3]), + .io_upIn_bits_tdata (io_up_bits_tdata[31:24]), + .io_upIn_bits_tlast (io_up_bits_tlast[3]), + .io_upIn_bits_tuser (io_up_bits_tuser[3]), + .io_upOut_ready (io_up_ready[2]), + .io_upOut_valid (io_up_valid[2]), + .io_upOut_bits_tdata (io_up_bits_tdata[31:24]), + .io_upOut_bits_tlast (io_up_bits_tlast[2]), + .io_upOut_bits_tuser (io_up_bits_tuser[2]), + + .io_timeStamp(timeStamp), + + .io_dSMdeq_0(1'b0), + .io_dSMdeq_1(1'b0), + .io_dSMdeq_2(1'b0), + .io_dSMdeq_3(1'b0), + .io_uSMenq_0(1'b0), + .io_uSMenq_1(1'b0), + .io_uSMenq_2(1'b0), + .io_uSMenq_3(1'b0), + + .io_sram_w_0_addrw(11'd0), + .io_sram_w_0_dataw(8'h0), + .io_sram_w_0_enw(1'b0), + .io_sram_w_1_addrw(11'd0), + .io_sram_w_1_dataw(8'h0), + .io_sram_w_1_enw(1'b0), + .io_sram_w_2_addrw(11'd0), + .io_sram_w_2_dataw(8'h0), + .io_sram_w_2_enw(1'b0), + .io_sram_w_3_addrw(11'd0), + .io_sram_w_3_dataw(8'h0), + .io_sram_w_3_enw(1'b0), + .io_sram_r_0_addrr(11'd0), + .io_sram_r_0_datar(), + .io_sram_r_0_enr(1'b0), + .io_sram_r_1_addrr(11'd0), + .io_sram_r_1_datar(), + .io_sram_r_1_enr(1'b0), + .io_sram_r_2_addrr(11'd0), + .io_sram_r_2_datar(), + .io_sram_r_2_enr(1'b0), + .io_sram_r_3_addrr(11'd0), + .io_sram_r_3_datar(), + .io_sram_r_3_enr(1'b0), + + .io_modeSel(1'b0), + + .io_req_valid(1'b0), + .io_req_bits_txAddr(15'h0), + .io_req_bits_rxAddr(15'h0), + .io_req_bits_length(12'd0), + .io_rsp_valid(), + .io_rsp_bits_isError(), + .io_rsp_bits_length() +); + +ShinTop s_ShinTop_slv3( + .clock(clock), + .reset(reset), + + .io_downIn_ready (io_down_ready[3]), + .io_downIn_valid (io_down_valid[3]), + .io_downIn_bits_tdata (io_down_bits_tdata[31:24]), + .io_downIn_bits_tlast (io_down_bits_tlast[3]), + .io_downIn_bits_tuser (io_down_bits_tuser[3]), + .io_downOut_ready (1'b0), + .io_downOut_valid (), + .io_downOut_bits_tdata(), + .io_downOut_bits_tlast(), + .io_downOut_bits_tuser(), + .io_upIn_ready (), + .io_upIn_valid (1'b0), + .io_upIn_bits_tdata (8'd0), + .io_upIn_bits_tlast (1'b0), + .io_upIn_bits_tuser (1'b0), + .io_upOut_ready (io_up_ready[3]), + .io_upOut_valid (io_up_valid[3]), + .io_upOut_bits_tdata (io_up_bits_tdata[31:24]), + .io_upOut_bits_tlast (io_up_bits_tlast[3]), + .io_upOut_bits_tuser (io_up_bits_tuser[3]), .io_timeStamp(timeStamp), @@ -175,294 +456,353 @@ end -reg [7:0] testDownData[0:1000]; + + + reg [7:0] dataBuf[0:2047]; + + initial begin + dataBuf[0] = 8'h00; + dataBuf[1] = 8'ha0;//heeader length 10 + dataBuf[2] = 8'h00; + dataBuf[3] = 8'h00; + + //子报文 + //设置顺序地址 + dataBuf[4] = 8'h0; //设备索引 + dataBuf[5] = 8'h0; //设备索引、类型 + dataBuf[6] = $random; //地址 + dataBuf[7] = $random; //地址 + dataBuf[8] = 8'hd0; //命令d 负载长度2 + dataBuf[9] = 8'd02; //负载长度2 + dataBuf[10] = 8'h0; //工作计数0 + dataBuf[11] = 8'h0; //工作计数0 + + dataBuf[12] = 8'h0; //负载 + dataBuf[13] = 8'h0; //负载 + end + + + + // for( integer i = 0; i < 8; i = i + 1 ) begin + // if( i != 5 ) begin + + // dataBuf[3 + 64 * i + 0] = $random; + // dataBuf[3 + 64 * i + 1] = $random; + // dataBuf[3 + 64 * i + 2] = $random; + // dataBuf[3 + 64 * i + 3] = $random; + // dataBuf[3 + 64 * i + 4] = 8'h0; + // dataBuf[3 + 64 * i + 5] = 8'd56; + // dataBuf[3 + 64 * i + 6] = $random; + // dataBuf[3 + 64 * i + 7] = $random; + + + // end + // end + initial begin - testDownData[0] = 8'hde; - testDownData[1] = 8'h0e; + #1000 + + for( integer i = 0; i < 14; i = i + 1 ) begin + @(posedge clock) #3 + sram_w_0_enw = 1'b1; + sram_w_0_addrw = i; + sram_w_0_dataw = dataBuf[i]; + end + + @(posedge clock) #3 + sram_w_0_enw = 1'b0; + sram_w_0_addrw = 15'h0; + sram_w_0_dataw = 8'h0; + + @(posedge clock) #3 + txCmf = 1'b1; + @(posedge clock) #3 + txCmf = 1'b0; + + @(posedge clock) #3 + req_valid = 1'b1; + req_bits_txAddr = 0; + req_bits_rxAddr = 0; + req_bits_length = 14; + + @(posedge clock) #3 + req_valid = 1'b0; end - -// reg [11:0] testDownDataCnt = 0; - - - - - - // always @(posedge clock) begin // end -initial begin - #1000 +// initial begin +// #1000 - s_ShinTop.slaveParser.localDevIndex = 3; //强制设备索引为3，测试子报文操作 +// s_ShinTop.slaveParser.localDevIndex = 3; //强制设备索引为3，测试子报文操作 - //主帧头 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h20; +// //主帧头 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h20; - @( io_downIn_valid & io_downIn_ready) +// @( io_downIn_valid & io_downIn_ready) - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h00; //heeader length 512 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h00; //heeader length 512 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h00; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h00; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h00; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h00; - //子报文 - for( integer i = 0; i < 8; i = i + 1 ) begin - if( i != 5 ) begin - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; +// //子报文 +// for( integer i = 0; i < 8; i = i + 1 ) begin +// if( i != 5 ) begin +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h0; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h0; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'd56; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'd56; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; - for( integer j = 0; j < 64-8; j = j+ 1 ) begin - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'ha5; //heeader length 512 - end - end else begin //第5个子报文操作 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h0; +// for( integer j = 0; j < 64-8; j = j+ 1 ) begin +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'ha5; //heeader length 512 +// end +// end else begin //第5个子报文操作 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h0; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'hC; //3号设备 类型空 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'hC; //3号设备 类型空 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h08; //地址 //SM0 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h08; //地址 //SM0 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h30; //地址 //偏置 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h30; //地址 //偏置 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h30; //命令3 长度56 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h30; //命令3 长度56 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'd56; //长度56 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'd56; //长度56 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; //工作计数 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; //工作计数 - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; //工作计数 +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; //工作计数 - for( integer j = 0; j < 64-8; j = j+ 1 ) begin - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = 8'h55; //heeader length 512 - end - end - end +// for( integer j = 0; j < 64-8; j = j+ 1 ) begin +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = 8'h55; //heeader length 512 +// end +// end +// end - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; - io_downIn_bits_tlast = 0; - io_downIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; +// io_downIn_bits_tlast = 0; +// io_downIn_bits_tuser = 0; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; - io_downIn_bits_tlast = 0; - io_downIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; +// io_downIn_bits_tlast = 0; +// io_downIn_bits_tuser = 0; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; - io_downIn_bits_tlast = 0; - io_downIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; +// io_downIn_bits_tlast = 0; +// io_downIn_bits_tuser = 0; - @(posedge clock) #3 - io_downIn_valid = 1; - io_downIn_bits_tdata = $random; - io_downIn_bits_tlast = 1; - io_downIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_downIn_valid = 1; +// io_downIn_bits_tdata = $random; +// io_downIn_bits_tlast = 1; +// io_downIn_bits_tuser = 0; - @(posedge clock) #3 - io_downIn_valid = 0; - io_downIn_bits_tlast = 0; +// @(posedge clock) #3 +// io_downIn_valid = 0; +// io_downIn_bits_tlast = 0; - #1000 - #1000 - #1000 - #1000 +// #1000 +// #1000 +// #1000 +// #1000 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h20; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h20; - @( io_upIn_valid & io_upIn_ready) +// @( io_upIn_valid & io_upIn_ready) - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h00; //heeader length 512 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h00; //heeader length 512 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h00; //heeader frameInfo +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h00; //heeader frameInfo - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h00; //heeader frameInfo +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h00; //heeader frameInfo - for( integer i = 0; i < 8; i = i + 1 ) begin - if( i != 5 ) begin - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; +// for( integer i = 0; i < 8; i = i + 1 ) begin +// if( i != 5 ) begin +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h0; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h0; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'd56; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'd56; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; - for( integer j = 0; j < 64-8; j = j+ 1 ) begin - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'ha5; //heeader length 512 - end - end else begin //第5个子报文操作 - // io_sram_r_datar = 8'hec; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h0; +// for( integer j = 0; j < 64-8; j = j+ 1 ) begin +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'ha5; //heeader length 512 +// end +// end else begin //第5个子报文操作 +// // io_sram_r_datar = 8'hec; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h0; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'hC; //3号设备 类型空 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'hC; //3号设备 类型空 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h10; //地址SM1 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h10; //地址SM1 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h10; //地址偏置 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h10; //地址偏置 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h30; //命令3 长度56 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h30; //命令3 长度56 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'd56; //长度56 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'd56; //长度56 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; //工作计数 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; //工作计数 - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; //工作计数 +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; //工作计数 - for( integer j = 0; j < 64-8; j = j+ 1 ) begin - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = 8'h55; //heeader length 512 - end - end - end +// for( integer j = 0; j < 64-8; j = j+ 1 ) begin +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = 8'h55; //heeader length 512 +// end +// end +// end - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; - io_upIn_bits_tlast = 0; - io_upIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; +// io_upIn_bits_tlast = 0; +// io_upIn_bits_tuser = 0; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; - io_upIn_bits_tlast = 0; - io_upIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; +// io_upIn_bits_tlast = 0; +// io_upIn_bits_tuser = 0; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; - io_upIn_bits_tlast = 0; - io_upIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; +// io_upIn_bits_tlast = 0; +// io_upIn_bits_tuser = 0; - @(posedge clock) #3 - io_upIn_valid = 1; - io_upIn_bits_tdata = $random; - io_upIn_bits_tlast = 1; - io_upIn_bits_tuser = 0; +// @(posedge clock) #3 +// io_upIn_valid = 1; +// io_upIn_bits_tdata = $random; +// io_upIn_bits_tlast = 1; +// io_upIn_bits_tuser = 0; - @(posedge clock) #3 - io_upIn_valid = 0; - io_upIn_bits_tlast = 0; -end +// @(posedge clock) #3 +// io_upIn_valid = 0; +// io_upIn_bits_tlast = 0; +// end