156 lines
3.5 KiB
Scala
156 lines
3.5 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class MasterParserIO extends Bundle{
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val downOut = Decoupled(new AXIS_Bundle(8))
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val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
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val sram_w = Flipped(new SRAM2kWRIO)
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val sram_r = Flipped(new SRAM2kRDIO)
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val req = Flipped(Valid(new Bundle{
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val txAddr = UInt(15.W)
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val rxAddr = UInt(15.W)
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val length = UInt(12.W)
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}))
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val rsp = Valid(new Bundle{
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val isError = Bool()
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val length = UInt(12.W)
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})
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val rxEnq = Output( Bool())
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val txDeq = Output( Bool())
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val trigAddr = Input( Vec(2, UInt(15.W)) )
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val timeStamp = Input(UInt(64.W))
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}
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abstract class MasterParserBase extends Module{
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val io: MasterParserIO = IO(new MasterParserIO)
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val txCnt = Reg(UInt(12.W))
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val txLen = Reg(UInt(11.W))
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val txAddr = Reg(UInt(15.W))
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val rxCnt = Reg(UInt(12.W))
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val rxLen = Reg(UInt(11.W))
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val rxAddr = Reg(UInt(15.W))
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val reqReady = RegInit(true.B)
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val txcrc = Module(new crc32_8)
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val rxcrc = Module(new crc32_8)
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// io.req.ready := reqReady
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when( io.req.fire ){
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reqReady := false.B
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} .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
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reqReady := true.B
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}
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when( io.req.fire ){
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txLen := io.req.bits.length
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rxLen := io.req.bits.length
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txCnt := 0.U
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} .elsewhen( io.downOut.fire ){
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txCnt := txCnt + 1.U
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}
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when( io.req.fire ){
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txAddr := io.req.bits.txAddr
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} .elsewhen( io.downOut.fire ){
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txAddr := txAddr + 1.U
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}
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when( io.req.fire ){
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rxAddr := io.req.bits.rxAddr
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} .elsewhen( io.upIn.fire ){
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rxAddr := rxAddr + 1.U
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}
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io.sram_r.enr :=
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io.req.fire | io.downOut.fire
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io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )
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io.downOut.valid := ~reqReady
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io.downOut.bits.tdata := Mux1H(Seq(
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( txCnt < txLen ) -> io.sram_r.datar,
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( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24),
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( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16),
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( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8),
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( txCnt === txLen + 3.U ) -> txcrc.io.crc( 7, 0),
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))
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io.downOut.bits.tuser := false.B
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io.downOut.bits.tlast := txCnt === (txLen + 3.U)
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val recCrcCheck = Reg(UInt(32.W))
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when( io.req.fire ){
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rxCnt := 0.U
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} .elsewhen( io.upIn.fire ){
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rxCnt := rxCnt + 1.U
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}
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io.upIn.ready := true.B
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io.sram_w.enw := io.upIn.fire
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io.sram_w.addrw := rxAddr
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io.sram_w.dataw := io.upIn.bits.tdata
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io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
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io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc
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io.rsp.bits.length := rxCnt + 1.U
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io.rxEnq := io.trigAddr(0) === txCnt & io.downOut.fire
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io.txDeq := io.trigAddr(1) === (rxCnt + 1.U) & io.upIn.fire
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txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
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txcrc.io.dataIn := io.downOut.bits.tdata
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txcrc.reset := reset.asBool | reqReady
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rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen
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rxcrc.io.dataIn := io.upIn.bits.tdata
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rxcrc.reset := reset.asBool | io.rsp.fire
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when( io.upIn.fire ){
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when( rxCnt === rxLen ){
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recCrcCheck := io.upIn.bits.tdata << 24
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} .elsewhen( rxCnt === (rxLen + 1.U) ){
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recCrcCheck := Cat( recCrcCheck(31,24), io.upIn.bits.tdata, recCrcCheck(15,0) )
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} .elsewhen( rxCnt === (rxLen + 2.U) ){
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recCrcCheck := Cat( recCrcCheck(31,16), io.upIn.bits.tdata, recCrcCheck( 7,0) )
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} .elsewhen( rxCnt === (rxLen + 3.U) ){
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recCrcCheck := Cat( recCrcCheck(31,8), io.upIn.bits.tdata )
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}
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}
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}
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class MasterParser extends MasterParserBase{
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} |