package BACK

import chisel3._
import chisel3.util._

class MasterParserIO extends Bundle{
  val downOut = Decoupled(new AXIS_Bundle(8))
  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )

  val sram_w = Flipped(new SRAM2kWRIO)
  val sram_r = Flipped(new SRAM2kRDIO)

  val req = Flipped(Valid(new Bundle{
    val txAddr    = UInt(15.W)
    val rxAddr    = UInt(15.W)
    val length  = UInt(12.W)
  }))
  val rsp = Valid(new Bundle{
    val isError = Bool()
    val length  = UInt(12.W)
  })

  val rxEnq = Output( Bool())
  val txDeq  = Output( Bool())

  val trigAddr = Input( Vec(2, UInt(15.W)) )

  val timeStamp = Input(UInt(64.W))

}

abstract class MasterParserBase extends Module{
  val io: MasterParserIO = IO(new MasterParserIO)

  val txCnt = Reg(UInt(12.W))
  val txLen = Reg(UInt(11.W))
  val txAddr = Reg(UInt(15.W))

  val rxCnt = Reg(UInt(12.W))
  val rxLen = Reg(UInt(11.W))
  val rxAddr = Reg(UInt(15.W))

  val reqReady = RegInit(true.B)


  val txcrc = Module(new crc32_8)
  val rxcrc = Module(new crc32_8)




  // io.req.ready := reqReady

  when( io.req.fire ){
    reqReady := false.B
  } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
    reqReady := true.B
  }

  when( io.req.fire ){
    txLen  := io.req.bits.length
    rxLen  := io.req.bits.length
    txCnt  := 0.U
  } .elsewhen( io.downOut.fire ){
    txCnt := txCnt + 1.U
  }

  when( io.req.fire ){
    txAddr := io.req.bits.txAddr
  } .elsewhen( io.downOut.fire ){
    txAddr := txAddr + 1.U
  }

  when( io.req.fire ){
    rxAddr := io.req.bits.rxAddr
  } .elsewhen( io.upIn.fire ){
    rxAddr := rxAddr + 1.U
  }



  io.sram_r.enr := 
    io.req.fire | io.downOut.fire

  io.sram_r.addrr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )

  io.downOut.valid := ~reqReady
  io.downOut.bits.tdata := Mux1H(Seq(
    ( txCnt  <  txLen       ) -> io.sram_r.datar,
    ( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24),
    ( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16),
    ( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8),
    ( txCnt === txLen + 3.U ) -> txcrc.io.crc( 7, 0),
  ))
  io.downOut.bits.tuser := false.B 
  io.downOut.bits.tlast := txCnt === (txLen + 3.U)



  val recCrcCheck = Reg(UInt(32.W))

  when( io.req.fire ){
    rxCnt := 0.U
  } .elsewhen( io.upIn.fire ){
    rxCnt := rxCnt + 1.U
  }


  io.upIn.ready := true.B

  io.sram_w.enw := io.upIn.fire
  io.sram_w.addrw := rxAddr
  io.sram_w.dataw := io.upIn.bits.tdata


  io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
  io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc
  io.rsp.bits.length  := rxCnt + 1.U



  io.rxEnq := io.trigAddr(0) === txCnt         & io.downOut.fire
  io.txDeq := io.trigAddr(1) === (rxCnt + 1.U) & io.upIn.fire




  txcrc.io.isEnable := io.downOut.fire & txCnt < txLen
  txcrc.io.dataIn   := io.downOut.bits.tdata
  txcrc.reset := reset.asBool | reqReady

  rxcrc.io.isEnable := io.upIn.fire & rxCnt < rxLen
  rxcrc.io.dataIn   := io.upIn.bits.tdata
  rxcrc.reset := reset.asBool | io.rsp.fire



  when( io.upIn.fire ){
    when( rxCnt === rxLen ){
      recCrcCheck := io.upIn.bits.tdata << 24
    } .elsewhen( rxCnt === (rxLen + 1.U) ){
      recCrcCheck := Cat( recCrcCheck(31,24), io.upIn.bits.tdata, recCrcCheck(15,0) )
    } .elsewhen( rxCnt === (rxLen + 2.U) ){
      recCrcCheck := Cat( recCrcCheck(31,16), io.upIn.bits.tdata, recCrcCheck( 7,0) )
    } .elsewhen( rxCnt === (rxLen + 3.U) ){
      recCrcCheck := Cat( recCrcCheck(31,8), io.upIn.bits.tdata )
    }
  }


}


class MasterParser extends MasterParserBase{

}