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看门狗挪到特质里

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This commit is contained in:
Ruige Lee
2025-08-06 15:23:43 +08:00
parent fd3bae6a04
commit 87c7bf6f41
1 changed files with 41 additions and 41 deletions
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82
src/main/scala/backBoard/shin/Interface.scala
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@@ -670,45 +670,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
}
val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
cReg.wdtStatus := Cat( wdtStatus.reverse )
for( i <- 0 until 8 ){
when( isEnW & addrw === "h400".U & dataw.extract(i) ){
wdtStatus(i) := false.B
} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
wdtStatus(i) := true.B
}
when( isEnW & addrw === "h401".U & dataw.extract(i) ){
wdtStatus(8+i) := false.B
} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
wdtStatus(8+i) := true.B
}
}
for( i <- 0 until 2 ){
when( isEnW & addrw === "h402".U & dataw.extract(i) ){
wdtStatus(16+i) := false.B
} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
wdtStatus(16+i) := true.B
}
}
cReg.wdtEnable :=
Cat(
RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
)
for( i <- 0 until 18 ){
cReg.wdtTarCnt(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
)
}
}
@@ -934,9 +896,47 @@ trait InterfaceSync{ this: InterfaceBase =>
}
// trait InterfaceWdt{ this: InterfaceBase =>
trait InterfaceWdt{ this: InterfaceBase =>
val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
cReg.wdtStatus := Cat( wdtStatus.reverse )
// }
for( i <- 0 until 8 ){
when( isEnW & addrw === "h400".U & dataw.extract(i) ){
wdtStatus(i) := false.B
} .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
wdtStatus(i) := true.B
}
when( isEnW & addrw === "h401".U & dataw.extract(i) ){
wdtStatus(8+i) := false.B
} .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
wdtStatus(8+i) := true.B
}
}
for( i <- 0 until 2 ){
when( isEnW & addrw === "h402".U & dataw.extract(i) ){
wdtStatus(16+i) := false.B
} .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
wdtStatus(16+i) := true.B
}
}
cReg.wdtEnable :=
Cat(
RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h405".U ),
RegEnable( dataw, 0.U, isEnW & addrw === "h404".U ),
)
for( i <- 0 until 18 ){
cReg.wdtTarCnt(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
)
}
}
trait InterfaceSystem{ this: InterfaceBase =>
io.isSoftReset :=
@@ -1277,7 +1277,7 @@ with InterfaceCheckSM
with InterfaceLVDSop
with InterfaceSync
with InterfaceStat
// with InterfaceWdt
with InterfaceWdt
with InterfaceSystem
with InterfaceEvent
{