From 87c7bf6f41e808680290f4050199b1c6d685f9bb Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 6 Aug 2025 15:23:43 +0800
Subject: [PATCH] =?UTF-8?q?=E7=9C=8B=E9=97=A8=E7=8B=97=E6=8C=AA=E5=88=B0?=
 =?UTF-8?q?=E7=89=B9=E8=B4=A8=E9=87=8C?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 82 +++++++++----------
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index bd31d84..0c9f8e3 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -670,45 +670,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   }
 
 
-  val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
-  cReg.wdtStatus := Cat( wdtStatus.reverse )
 
-  for( i <- 0 until 8 ){
-    when( isEnW & addrw === "h400".U & dataw.extract(i) ){
-      wdtStatus(i) := false.B
-    } .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
-      wdtStatus(i) := true.B
-    }
-    when( isEnW & addrw === "h401".U & dataw.extract(i) ){
-      wdtStatus(8+i) := false.B
-    } .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
-      wdtStatus(8+i) := true.B
-    }
-  }
-  for( i <- 0 until 2 ){
-    when( isEnW & addrw === "h402".U & dataw.extract(i) ){
-      wdtStatus(16+i) := false.B
-    } .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
-      wdtStatus(16+i) := true.B
-    }
-  }
-
-  cReg.wdtEnable := 
-    Cat(
-      RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
-      RegEnable( dataw,            0.U, isEnW & addrw === "h405".U ),
-      RegEnable( dataw,            0.U, isEnW & addrw === "h404".U ),
-    )
-
-  for( i <- 0 until 18 ){
-    cReg.wdtTarCnt(i) :=
-      Cat(
-        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
-        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
-        RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
-        RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
-      )
-  }
 
 }
 
@@ -934,9 +896,47 @@ trait InterfaceSync{ this: InterfaceBase =>
 
 }
 
-// trait InterfaceWdt{ this: InterfaceBase =>
+trait InterfaceWdt{ this: InterfaceBase =>
+  val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
+  cReg.wdtStatus := Cat( wdtStatus.reverse )
 
-// }
+  for( i <- 0 until 8 ){
+    when( isEnW & addrw === "h400".U & dataw.extract(i) ){
+      wdtStatus(i) := false.B
+    } .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){
+      wdtStatus(i) := true.B
+    }
+    when( isEnW & addrw === "h401".U & dataw.extract(i) ){
+      wdtStatus(8+i) := false.B
+    } .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){
+      wdtStatus(8+i) := true.B
+    }
+  }
+  for( i <- 0 until 2 ){
+    when( isEnW & addrw === "h402".U & dataw.extract(i) ){
+      wdtStatus(16+i) := false.B
+    } .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
+      wdtStatus(16+i) := true.B
+    }
+  }
+
+  cReg.wdtEnable := 
+    Cat(
+      RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
+      RegEnable( dataw,            0.U, isEnW & addrw === "h405".U ),
+      RegEnable( dataw,            0.U, isEnW & addrw === "h404".U ),
+    )
+
+  for( i <- 0 until 18 ){
+    cReg.wdtTarCnt(i) :=
+      Cat(
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
+        RegEnable( dataw, 0.U, isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
+      )
+  }
+}
 
 trait InterfaceSystem{ this: InterfaceBase =>
   io.isSoftReset :=
@@ -1277,7 +1277,7 @@ with InterfaceCheckSM
 with InterfaceLVDSop
 with InterfaceSync
 with InterfaceStat
-// with InterfaceWdt
+with InterfaceWdt
 with InterfaceSystem
 with InterfaceEvent
 {