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综合尝试，需要面积优化

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RuigeLee
2024-10-30 18:05:41 +08:00
parent 21c34c4104
commit 82d99c4000
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -65,7 +65,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
beatBytes = 32/8))) beatBytes = 32/8)))
val sram = LazyModule(new TLRAM( val sram = LazyModule(new TLRAM(
address = AddressSet(0x80000000L, 0xffffL), address = AddressSet(0x80000000L, 0xfffL),
cacheable = false, cacheable = false,
executable = true, executable = true,
atomics = false, atomics = false,

2
src/test/scala/gcd/test.scala
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@@ -61,7 +61,7 @@ object testModule extends App {
val cfg = new BackCfg val cfg = new BackCfg
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq( (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
ChiselGeneratorAnnotation(() => { ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new BackSys()(cfg)) val soc = LazyModule(new BackSys()(cfg))
soc.module soc.module