diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala
index 2878f4d..821615a 100644
--- a/src/main/scala/backBoard/pico/BackSystem.scala
+++ b/src/main/scala/backBoard/pico/BackSystem.scala
@@ -65,7 +65,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
     beatBytes = 32/8)))
 
   val sram = LazyModule(new TLRAM(
-    address = AddressSet(0x80000000L, 0xffffL),
+    address = AddressSet(0x80000000L, 0xfffL),
     cacheable = false,
     executable = true,
     atomics = false,
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index 01fd9e3..40843a0 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -61,7 +61,7 @@ object testModule extends App {
 
   val cfg = new BackCfg
 
-  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
     val soc = LazyModule(new BackSys()(cfg))
     soc.module