From 82d99c40001fea2fd48235427a619e252f9c60ff Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 30 Oct 2024 18:05:41 +0800 Subject: [PATCH] =?UTF-8?q?=E7=BB=BC=E5=90=88=E5=B0=9D=E8=AF=95=EF=BC=8C?= =?UTF-8?q?=E9=9C=80=E8=A6=81=E9=9D=A2=E7=A7=AF=E4=BC=98=E5=8C=96?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/pico/BackSystem.scala | 2 +- src/test/scala/gcd/test.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index 2878f4d..821615a 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -65,7 +65,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter beatBytes = 32/8))) val sram = LazyModule(new TLRAM( - address = AddressSet(0x80000000L, 0xffffL), + address = AddressSet(0x80000000L, 0xfffL), cacheable = false, executable = true, atomics = false, diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 01fd9e3..40843a0 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -61,7 +61,7 @@ object testModule extends App { val cfg = new BackCfg - (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq( + (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq( ChiselGeneratorAnnotation(() => { val soc = LazyModule(new BackSys()(cfg)) soc.module