综合尝试，需要面积优化

2024-10-30 18:05:41 +08:00
parent 21c34c4104
commit 82d99c4000
2 changed files with 2 additions and 2 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -61,7 +61,7 @@ object testModule extends App {

  val cfg = new BackCfg

-  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--gen-mem-verilog", "true", "--show-registrations", "--full-stacktrace", "--target-dir", "generated/cdr/", "-e", "verilog") ++ args, Seq(
      ChiselGeneratorAnnotation(() => {
    val soc = LazyModule(new BackSys()(cfg))
    soc.module