综合尝试，需要面积优化

2024-10-30 18:05:41 +08:00
parent 21c34c4104
commit 82d99c4000
2 changed files with 2 additions and 2 deletions
--- a/src/main/scala/backBoard/pico/BackSystem.scala
+++ b/src/main/scala/backBoard/pico/BackSystem.scala
@@ -65,7 +65,7 @@ class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameter
    beatBytes = 32/8)))

  val sram = LazyModule(new TLRAM(
-    address = AddressSet(0x80000000L, 0xffffL),
+    address = AddressSet(0x80000000L, 0xfffL),
    cacheable = false,
    executable = true,
    atomics = false,