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修复合并过程中位宽错误

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RuigeLee
2025-09-07 22:35:32 +08:00
parent a410c7ba67
commit 777ca7319b
1 changed files with 1 additions and 1 deletions
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src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -81,7 +81,7 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
val clearCnt = RegInit(0.U(4.W)) val clearCnt = RegInit(0.U(4.W))
val checkCnt = RegInit(0.U(4.W)) val checkCnt = RegInit(0.U(4.W))
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W )) val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W ))
val isLock = RegInit(false.B) val isLock = RegInit(false.B)
when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){ when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){