From 777ca7319b6ba51bdbb4990affb50c3afb307aab Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sun, 7 Sep 2025 22:35:32 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E5=90=88=E5=B9=B6=E8=BF=87?= =?UTF-8?q?=E7=A8=8B=E4=B8=AD=E4=BD=8D=E5=AE=BD=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 37b997d..63d396a 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -81,7 +81,7 @@ class CDRInMultiSample extends Module with RequireAsyncReset{ val clearCnt = RegInit(0.U(4.W)) val checkCnt = RegInit(0.U(4.W)) - val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W )) + val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W )) val isLock = RegInit(false.B) when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){