diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 37b997d..63d396a 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -81,7 +81,7 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
 
   val clearCnt = RegInit(0.U(4.W))
   val checkCnt = RegInit(0.U(4.W))
-  val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
+  val arbCali = RegInit(0.U( (log2Ceil(8*clkNum)).W ))
   val isLock = RegInit(false.B)
 
   when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){