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FPGA测试通过

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This commit is contained in:
Ruige Lee
2025-08-27 17:06:31 +08:00
parent 58ad17ce79
commit 706b9f17e5
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -146,7 +146,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
}) })
when( ~isLock ){ when( ~isLock ){
for( i <- 50 until 50+16 ){ for( i <- 0 until 16 ){
val j = 50+16 - i - 1 val j = 50+16 - i - 1
when( flitReg(j) ^ flitReg(j+1) ){ when( flitReg(j) ^ flitReg(j+1) ){
arbLock := j.U arbLock := j.U
@@ -174,7 +174,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
} }
when( ~isLock ){ when( ~isLock ){
for( i <- 50 until 50+16 ){ for( i <- 0 until 16 ){
val j = 50+16 - i - 1 val j = 50+16 - i - 1
when( flitReg(j) ^ flitReg(j+1) ){ when( flitReg(j) ^ flitReg(j+1) ){
isLock := true.B isLock := true.B