From 706b9f17e5527c2f9b7211040cf5477813b67521 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 27 Aug 2025 17:06:31 +0800
Subject: [PATCH] =?UTF-8?q?FPGA=E6=B5=8B=E8=AF=95=E9=80=9A=E8=BF=87?=
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---
 src/main/scala/backBoard/ebus/CDRIn.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 9bbbf98..b1db89b 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -146,7 +146,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
     })
 
   when( ~isLock ){
-    for( i <- 50 until 50+16 ){
+    for( i <- 0 until 16 ){
       val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         arbLock := j.U
@@ -174,7 +174,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
   }
 
   when( ~isLock ){
-    for( i <- 50 until 50+16 ){
+    for( i <- 0 until 16 ){
       val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         isLock := true.B