diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 9bbbf98..b1db89b 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -146,7 +146,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
     })
 
   when( ~isLock ){
-    for( i <- 50 until 50+16 ){
+    for( i <- 0 until 16 ){
       val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         arbLock := j.U
@@ -174,7 +174,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
   }
 
   when( ~isLock ){
-    for( i <- 50 until 50+16 ){
+    for( i <- 0 until 16 ){
       val j = 50+16 - i - 1
       when( flitReg(j) ^ flitReg(j+1) ){
         isLock := true.B