产生初始化完成，传输完成，错误中断信号，宽度一个周期(10MHZ)

2024-03-20 10:26:31 +08:00
parent 8d97fff560
commit 5f61a4265e
2 changed files with 23 additions and 19 deletions
--- a/src/main/verilog/backBoardMstTop.v
+++ b/src/main/verilog/backBoardMstTop.v
@@ -18,7 +18,9 @@ module master_top(
  input         io_FSMC_csn,
  input         io_FSMC_rdn,
  input         io_FSMC_wrn,
-  input         io_FSMC_advn
+  input         io_FSMC_advn,
+
+  output        interrupt
 );

 wire [15:0] io_FSMC_ADIn;
@@ -150,7 +152,9 @@ BackBoardMst i_BackBoardMst(
    .io_ides_fclk(clk_400m_a),

    .io_lvds_down_dout(lvds_down_dout),
-    .io_lvds_up_din(lvds_up_din)
+    .io_lvds_up_din(lvds_up_din),
+
+    .io_interrupt(interrupt)
 );