From 5f61a4265e1583d1dbab51063fa161b85629a9e9 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 20 Mar 2024 10:26:31 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BA=A7=E7=94=9F=E5=88=9D=E5=A7=8B=E5=8C=96?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 34 ++++++++++-----------
 src/main/verilog/backBoardMstTop.v          |  8 +++--
 2 files changed, 23 insertions(+), 19 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index a02f0b6..8ef8a7b 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -30,11 +30,7 @@ val reset_calib = Input(Bool())
   val lvds_down_dout = Output(Bool())
   val lvds_up_din    = Input(Bool())
 
-  val cdrErr         = Output(Bool())
-  val crcErr         = Output(Bool())
-  val linkErr        = Output(Bool())
-
-  // val interrupt = Output(Bool())
+  val interrupt = Output(Bool())
 
 }
 
@@ -78,6 +74,7 @@ class BackBoardMstBase extends Module{ //10M
   val slvNum  = RegInit(0.U(6.W))
   val slvOffLine = RegInit(0.U(6.W))
   val testReg = RegInit("haa55".U(16.W))
+  val interrupt = RegInit(false.B); io.interrupt := interrupt
 
   lvdsMst.io.rst_n       := ~reset.asBool
   lvdsMst.io.reset_calib := io.reset_calib
@@ -100,10 +97,10 @@ class BackBoardMstBase extends Module{ //10M
   mirrorUp.io.clockr := io.ides_pclk.asBool   //100M
 
 
+  when(interrupt === true.B){
+    interrupt := false.B
+  }
 
-  io.cdrErr  := statusCDRErr
-  io.crcErr  := statusCRCErr
-  io.linkErr := statusLinkErr
 
 }
 
@@ -134,20 +131,15 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     val regOut = Wire(UInt(16.W))
 
 
-    // val fsmcCSWRSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.wrn, 3, false.B, true.B )
-    // val fsmcCSRDSync = ShiftRegisters( ~io.FSMC.csn & ~io.FSMC.rdn, 3, false.B, true.B )
-    
 
 
-
-    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0) //~fsmcCSWRSync(2) & fsmcCSWRSync(1)
+    mirrorDown.io.enw    := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0)
     mirrorDown.io.addrw  := activeAddr
     mirrorDown.io.dataw  := io.FSMC.ADIn
 
-    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0) // ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
+    mirrorUp.io.enr    := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0)
     mirrorUp.io.addrr  := activeAddr
 
-
     io.FSMC.ADOut   := Mux( isAccessReg, regOut, mirrorUp.io.datar)
 
     regOut := Mux1H(Seq(
@@ -354,8 +346,10 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
         stateCur := 8.U
         synchCnt := 0.U
       } .otherwise{
+        stateCur := 14.U
         statusInit  := true.B
         ctrlInit    := false.B
+        interrupt   := true.B
       }
 
     } .elsewhen( stateCur === 8.U ){   //synch
@@ -397,10 +391,13 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
         stateCur := 8.U
       }
     } .elsewhen( stateCur === 13.U ){
+      stateCur := 14.U
       statusSynch := true.B
       statusInit  := true.B
       ctrlSynch   := false.B
       ctrlInit    := false.B
+      interrupt   := true.B
+    } .elsewhen( stateCur === 14.U ){
 
     } .elsewhen( stateCur === 15.U ){
 
@@ -419,8 +416,6 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
 
   val trigger = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
 
-  // val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
-
   when(ctrlTransmit){
     when( trigger ){  //reset
       stateCur := 0.U
@@ -455,7 +450,9 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
       }
 
     } .elsewhen( stateCur === 3.U ){
+      stateCur := 4.U
       ctrlTransmit := false.B
+      interrupt    := true.B
     } .otherwise{
 
     }
@@ -492,14 +489,17 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
   when( lvdsMst.io.closed_loop_err ){
     slvOffLine    := lvdsMst.io.link_err_location(5,0)
     statusLinkErr := true.B
+    interrupt     := true.B
   }
 
   when( lvdsMst.io.upstream_cdr_err ){
     statusCDRErr := true.B
+    interrupt     := true.B
   }
 
   when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
     statusCRCErr := true.B
+    interrupt     := true.B
   }
 
 }
diff --git a/src/main/verilog/backBoardMstTop.v b/src/main/verilog/backBoardMstTop.v
index a8250ee..68a5487 100644
--- a/src/main/verilog/backBoardMstTop.v
+++ b/src/main/verilog/backBoardMstTop.v
@@ -18,7 +18,9 @@ module master_top(
   input         io_FSMC_csn,
   input         io_FSMC_rdn,
   input         io_FSMC_wrn,
-  input         io_FSMC_advn
+  input         io_FSMC_advn,
+
+  output        interrupt
 );
 
 wire [15:0] io_FSMC_ADIn;
@@ -150,7 +152,9 @@ BackBoardMst i_BackBoardMst(
     .io_ides_fclk(clk_400m_a),
 
     .io_lvds_down_dout(lvds_down_dout),
-    .io_lvds_up_din(lvds_up_din)
+    .io_lvds_up_din(lvds_up_din),
+
+    .io_interrupt(interrupt)
 );