175 lines
3.1 KiB
Verilog
175 lines
3.1 KiB
Verilog
////////////////////////
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//LVDS-BUS SYSTEM DEMO//
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////////////////////////
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module master_top(
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input resetn,
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input clock,
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input lvds_up_din_p,
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input lvds_up_din_n,
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output lvds_down_dout_p,
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output lvds_down_dout_n,
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inout [15:0] io_FSMC_AD,
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input io_FSMC_csn,
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input io_FSMC_rdn,
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input io_FSMC_wrn,
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input io_FSMC_advn,
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output interrupt
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);
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wire [15:0] io_FSMC_ADIn;
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wire [15:0] io_FSMC_ADOut;
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wire io_FSMC_ADOEn;
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wire clk_400m;
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wire clk_400m_a;
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wire clk_100m;
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wire clk_100m_a;
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wire clk_50m;
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wire clk_50m_a;
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wire clk_10m_a;
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reg rst_n;
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wire lvds_down_dout;
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wire lvds_up_din;
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reg rstn_d;
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wire reset_calib;
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wire lock_o;
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wire reset_stop;
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always@(posedge clk_10m_a) begin
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rstn_d <= resetn;
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rst_n <= rstn_d;
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end
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Gowin_PLLO Gowin_PLLO(
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.lock(lock_o),
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.clkouta(clk_400m),
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.clkin(clock)
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);
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TLVDS_OBUF lvds_downstream_out(
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.O(lvds_down_dout_p),
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.OB(lvds_down_dout_n),
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.I(lvds_down_dout)
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);
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TLVDS_IBUF lvds_upstream_in(
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.O(lvds_up_din),
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.I(lvds_up_din_p),
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.IB(lvds_up_din_n)
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);
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DHCEN dhcen_inst (
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.CLKIN(clk_400m),
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.CE(reset_stop),
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.CLKOUT(clk_400m_a)
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);
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//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
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oser_rst u_oser_rst(
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.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
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.rst_n(rst_n),
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.pll_lock(lock_o), // trigged by PLL Lock
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.reset_stop(reset_stop), // for DHCEN CE
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.reset_calib(reset_calib), // for IDES and CLKDIV reset
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.set_calib(),
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.ready()
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);
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defparam Inst4_CLKDIVC.DIV_MODE="4";
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defparam Inst4_CLKDIVC.GSREN="false";
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CLKDIV Inst4_CLKDIVC(
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.RESETN (~reset_calib),
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.HCLKIN (clk_400m_a),
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.CALIB (1'b0 ),
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.CLKOUT (clk_100m_a)
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);
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defparam Inst2_CLKDIVC.DIV_MODE="2";
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defparam Inst2_CLKDIVC.GSREN="false";
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CLKDIV Inst2_CLKDIVC(
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.RESETN (~reset_calib),
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.HCLKIN (clk_100m_a),
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.CALIB (1'b0 ),
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.CLKOUT (clk_50m_a)
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);
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defparam Inst5_CLKDIVC.DIV_MODE="5";
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defparam Inst5_CLKDIVC.GSREN="false";
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CLKDIV Inst5_CLKDIVC(
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.RESETN (~reset_calib),
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.HCLKIN (clk_50m_a),
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.CALIB (1'b0 ),
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.CLKOUT (clk_10m_a)
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);
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BackBoardMst i_BackBoardMst(
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.io_FSMC_ADIn (io_FSMC_ADIn),
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.io_FSMC_ADOut(io_FSMC_ADOut),
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.io_FSMC_ADOEn(io_FSMC_ADOEn),
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.io_FSMC_csn(io_FSMC_csn),
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.io_FSMC_rdn(io_FSMC_rdn),
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.io_FSMC_wrn(io_FSMC_wrn),
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.io_FSMC_advn(io_FSMC_advn),
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// .io_FSMC_ADIn ('d0),
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// .io_FSMC_ADOut(),
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// .io_FSMC_ADOEn(),
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// .io_FSMC_csn(1'b1),
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// .io_FSMC_rdn(1'b1),
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// .io_FSMC_wrn(1'b1),
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// .io_FSMC_advn(1'b1),
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.reset(~rst_n),
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.clock(clk_10m_a),
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.io_reset_calib(reset_calib),
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.io_oser_pclk(clk_10m_a),
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.io_oser_fclk(clk_50m_a),
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.io_ides_pclk(clk_100m_a),
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.io_ides_fclk(clk_400m_a),
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.io_lvds_down_dout(lvds_down_dout),
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.io_lvds_up_din(lvds_up_din),
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.io_interrupt(interrupt)
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);
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generate
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for( genvar i = 0; i < 16; i = i + 1 ) begin
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IOBUF uut(
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.O(io_FSMC_ADIn[i]),
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.IO(io_FSMC_AD[i]),
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.I(io_FSMC_ADOut[i]),
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.OEN(~io_FSMC_ADOEn)
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);
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end
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endgenerate
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endmodule
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