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尝试修复读取数据错位问题

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Ruige Lee
2025-05-22 10:16:00 +08:00
parent 5723b4f127
commit 5e03cc4146
2 changed files with 4 additions and 4 deletions
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2
src/main/scala/backBoard/shin/Interface.scala
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@@ -405,7 +405,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
)) ))
datar := MuxCase( 0.U, Array( datar := MuxCase( 0.U, Array(
((addrr & "hF800".U) === "h0000".U) -> AcquireReg(addr = addrr), ((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar, ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
((addrr & "hF800".U) === "h1000".U) -> 0.U, ((addrr & "hF800".U) === "h1000".U) -> 0.U,
((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar, ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,

6
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -71,7 +71,7 @@ abstract class SpiInterfaceBase extends Module{
io.addrw := addrw io.addrw := addrw
// io.addrSel := // io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况 // Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
val readData = RegEnable(io.datar, io.isEnR) // val readData = RegEnable(io.datar, io.isEnR)
when( shiftCSn(2) & ~shiftCSn(1) ){ when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -152,7 +152,7 @@ class SSpiInterface extends SpiInterfaceBase{
when((byteSel === 1.U || byteSel === 2.U) ){ when((byteSel === 1.U || byteSel === 2.U) ){
exRego := 0.U //地址1，cmd exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){ } .elsewhen( isSpiRead ){
exRego := readData exRego := io.datar
} }
}.otherwise{ }.otherwise{
exRego := exRego << 1 exRego := exRego << 1
@@ -195,7 +195,7 @@ class QSpiInterface extends SpiInterfaceBase{
when((byteSel === 1.U || byteSel === 2.U) ){ when((byteSel === 1.U || byteSel === 2.U) ){
exRego := 0.U //地址1，cmd exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){ } .elsewhen( isSpiRead ){
exRego := readData exRego := io.datar
} }
}.otherwise{ }.otherwise{
exRego := exRego << 4 exRego := exRego << 4