From 5e03cc4146192671682162edbda32c4620c52d20 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 22 May 2025 10:16:00 +0800 Subject: [PATCH] =?UTF-8?q?=E5=B0=9D=E8=AF=95=E4=BF=AE=E5=A4=8D=E8=AF=BB?= =?UTF-8?q?=E5=8F=96=E6=95=B0=E6=8D=AE=E9=94=99=E4=BD=8D=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 2 +- src/main/scala/backBoard/shin/SpiInterface.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 5dd5b64..3fcb5b5 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -405,7 +405,7 @@ trait InterfaceMCUop{ this: InterfaceBase => )) datar := MuxCase( 0.U, Array( - ((addrr & "hF800".U) === "h0000".U) -> AcquireReg(addr = addrr), + ((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ), ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar, ((addrr & "hF800".U) === "h1000".U) -> 0.U, ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar, diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index d7d9b61..8a9c339 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -71,7 +71,7 @@ abstract class SpiInterfaceBase extends Module{ io.addrw := addrw // io.addrSel := // Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况 - val readData = RegEnable(io.datar, io.isEnR) + // val readData = RegEnable(io.datar, io.isEnR) when( shiftCSn(2) & ~shiftCSn(1) ){ @@ -152,7 +152,7 @@ class SSpiInterface extends SpiInterfaceBase{ when((byteSel === 1.U || byteSel === 2.U) ){ exRego := 0.U //地址1，cmd } .elsewhen( isSpiRead ){ - exRego := readData + exRego := io.datar } }.otherwise{ exRego := exRego << 1 @@ -195,7 +195,7 @@ class QSpiInterface extends SpiInterfaceBase{ when((byteSel === 1.U || byteSel === 2.U) ){ exRego := 0.U //地址1，cmd } .elsewhen( isSpiRead ){ - exRego := readData + exRego := io.datar } }.otherwise{ exRego := exRego << 4